ASAHI KASEI
[AK4620B]
AK4620B
24-Bit 192kHz Audio CODEC with IPGA
GENERAL DESCRIPTION
The AK4620B is a high performance 24-bit CODEC that supports up to 192kHz record and playback. The
on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit
architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise
and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4620B has
an input Programmable Gain Amplifier and is ideal for Pro Audio sound cards, Digital Audio Workstations,
DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.
FEATURES
•
24-bit 2-channel ADC
- Selectable Single-ended or Differential Input
- High Performance Linear Phase Digital Anti-Alias Filter
Passband: 0 ~ 20.25kHz (@fs=44.1kHz)
Ripple: ± 0.005dB
Stopband Attenuation: 100dB
- S/(N+D): 90dB (single-ended)
100dB (differential)
- S/N: 110dB (single-ended)
113dB (differential)
- Digital High-pass Filter for Offset Cancellation
- Input PGA: 0dB to +18dB, 0.5dB/step (for single-ended input)
- Input Digital Attenuator: 0dB to – 63dB, 0.5dB/step
- Overflow Flag
2
- Audio Interface Format: MSB justified or I S
•
24-bit 2-channel DAC
- 24-bit 8 times Oversampling Linear Phase Digital Filter
Ripple: ±0.005dB
Stopband Attenuation: 75dB
- Switched-cap Low Pass Filter
- Differential Outputs
- S/(N+D): 97dB
- S/N: 115dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling
- Output Digital Attenuator: Linear 255 steps
- Soft Mute
- Zero Detection Function
2
- Audio interface format: MSB justified, LSB justified, I S, or DSD
•
High Jitter Tolerance
•
Sampling Rate: Up to 216kHz
• µP
Interface: 3-wire Serial Interface
•
Master Clock
- 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
•
Power Supply: 5V ± 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital)
•
Small 30-pin VSOP package
•
Ta: -10 to 70
°C
MS0401-E-00
-1-
2005/07
ASAHI KASEI
[AK4620B]
Block Diagram
ADMODE
AINL+
VD
VT
DGND
AINL-/NC
ADC
AINR+
HPF
DATT
PDN
LRCK
BICK
SDTO
SDTI
MCLK
DFS0
DAC
DATT
SMUTE
Control Register I/F
P/S
AINR-/NC
OVFL/DZFL
OVFR/DZFR
AOUTL+
AOUTL-
AOUTR+
AOUTR-
OVF
Audio I/F
Controller
VCOM
VREF
VA
AGND
DEM0
CSN/
DIF
CCLK/
CKS1
CDTI/
CKS0
Figure 1. Block Diagram
•
Compatibility with AK4528 / AK4524
Function
Max fs
ADC Inputs
Input analog PGA
Input digital ATT
ADC S/(N+D)
ADC DR, S/N
ADC Digital Filter SA
ADC Overflow detection
DAC S/(N+D)
DAC DR, S/N
Output digital Attenuator
DAC DSD mode
DAC Zero-data detection
X’tal Oscillating Circuit
Master Mode
Parallel Mode
AK4524
96kHz
Single-ended
0dB ~ +18dB
0.5dB/step
Mute, -72dB ~ 0dB
Pseudo-log step
90dB
100dB
75dB
-
94dB
110dB
Mute, -72dB ~ 0dB
Pseudo-log step
-
-
X
X
-
AK4528
108kHz
Differential
-
Mute, -72dB ~ 0dB
Pseudo-log step
94dB
108dB
75dB
-
94dB
110dB
Mute, -72dB ~ 0dB
Pseudo-log step
-
-
-
-
X
AK4620B
216kHz
Single-ended
Differential
0 ~ +18dB
-
0.5dB/step
Mute,-63.5dB ~ 0dB Mute,-63.5dB ~ 0dB
0.5dB/step
0.5dB/step
90dB
100dB
110dB
113dB
100dB
X
97dB
115dB
Mute, -48dB ~ 0dB Mute, -48dB ~ 0dB
Linear 256 steps
Linear 256 steps
X
X
-
-
X
X: Available, -: NOT available
MS0401-E-00
-2-
2005/07
ASAHI KASEI
[AK4620B]
Ordering Guide
AK4620BVF
AKD4620B
-10∼+70°C
Evaluation Board
30pin VSOP (0.65mm pitch)
Pin Layout
VCOM
AINR+
AINR-/NC
AINL+
AINL-/NC
VREF
AGND
VA
P/S
MCLK
LRCK/DSDR
BICK/DCLK
SDTO
SDTI/DSDL
OVFR/DZFR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
AOUTR+
AOUTR-
AOUTL+
AOUTL-
DGND
VD
VT
ADMODE
DEM0
PDN
DFS0
CSN/DIF
CCLK/CKS1
CDTI/CKS0
OVFL/DZFL
Top
View
25
24
23
22
21
20
19
18
17
16
MS0401-E-00
-3-
2005/07
ASAHI KASEI
[AK4620B]
PIN/FUNCTION
No.
1
2
3
4
5
Pin Name
VCOM
AINR+
AINR-
AINL+
AINL-
I/O
O
I
I
I
I
I
I
Function
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin
Rch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Lch Positive Input Pin
Lch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
VA.
Analog Ground Pin
Analog Power Supply Pin, 4.75
∼
5.25V
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Master Clock Input Pin
Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Clock Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Output Pin
Audio Serial Data Input Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode)
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Control Data Input Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Control Data Clock Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Chip Select Pin in Serial Mode (in Serial Mode)
Digital Audio Interface Select Pin (in Parallel Mode)
“L”: 24bit MSB justified, “H”: I
2
S compatible
Double Speed Sampling Mode Pin
Power-Down Mode Pin
“L”: Power down reset and initialize the control register, “H”: Power up
De-emphasis Control Pin
Analog Input Mode Select Pin
“L”: Single-ended Input & IPGA Enable
“H”: Differential Input & IPGA Bypass
6
7
8
9
10
11
12
13
14
15
16
17
18
VREF
AGND
VA
P/S
MCLK
LRCK
DSDR
BICK
DCLK
SDTO
SDTI
DSDL
OVFR
DZFR
OVFL
DZFL
CDTI
CKS0
CCLK
CKS1
CSN
I
-
-
I
I
I
I
I
I
O
I
I
O
O
O
O
I
I
I
I
I
I
I
I
I
I
19
20
21
22
23
DIF
DFS0
PDN
DEM0
ADMODE
MS0401-E-00
-4-
2005/07
ASAHI KASEI
[AK4620B]
PIN/FUNCTION (Continued)
24
25
26
27
28
29
30
VT
VD
DGND
AOUTL-
AOUTL+
AOUTR-
AOUTR+
-
-
-
O
O
O
O
Input Buffer Tolerant Pin, 3.0
∼
5.25V
Digital Power Supply Pin, 3.0
∼
3.6V
Digital Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Note. Do not allow digital input pins (P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0,
CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins) to float.
Handling of Unused Pin
The unused I/O pin should be processed appropriately as below.
Classification
Pin Name
AINL+, AINL-/NC, AINR+, AINR+NC
AINL+, AINL-/NC
AINR+, AINR-/NC
Analog Output
Digital Input
Digital Output
AOUTL+, AOUTL-, AOUTR+,
AOUTR-
DEM0
OVFL/DZFL, OVFR/DZFR
Setting
These pins should be open when ADMODE pin = “L”.
AINL+ pin is connected to AINL-/NC pin when
ADMODE pin = “H”.
AINR+ pin is connected to AINR-/NC pin when
ADMODE pin = “H”.
These pins should be open.
This pin should be connected to DVSS.
These pins should be open.
Analog Input
MS0401-E-00
-5-
2005/07
嵌入式系统
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