HSP9501
TM
Data Sheet
January 1999
File Number
2786.4
Programmable Data Buffer
The HSP9501 is a 10-Bit wide programmable data buffer
designed for use in high speed digital systems. Two different
modes of operation can be selected through the use of the
MODSEL input. In the delay mode, a programmable data
pipeline is created which can provide 2 to 1281 clock cycles
of delay between the input and output data. In the data
recirculate mode, the output data path is internally routed
back to the input to provide a programmable circular buffer.
The length of the buffer or amount of delay is programmed
through the use of the 11-bit Length Control Input Port (LC0-
10) and the Length Control Enable (LCEN). An 11-bit value
is applied to the LC0-10 inputs, LCEN is asserted, and the
next selected clock edge loads the new count value into the
Length Control Register. The delay path of the HSP9501
consists of two registers with a programmable delay RAM
between them, therefore, the value programmed into the
Length Control Register is the desired length - 2. The range
of values which can be programmed into the Length Control
Register are from 0 to 1279, which in turn results in an
overall range of programmable delays from 2 to 1281.
Clock select logic is provided to allow the use of a positive or
negative edge system clock as the CLK input to the
HSP9501. The active edge of the CLK input is controlled
through the use of the CLKSEL input. All synchronous timing
(i.e., data setup, hold, and output delays) are relative to the
clock edge selected by CLKSEL. An additional clock enable
input (CLKEN) provides a means of disabling the internal
clock and holding the existing contents temporarily. All
outputs of the HSP9501 are three-state outputs to allow
direct interfacing to system or multi-use busses.
The HSP9501 is recommended for digital video processing
or any applications which require a programmable delay or
circular data buffer.
Features
• DC to 32MHz Operating Frequency
• Programmable Buffer Length from 2 to 1281 Words
• Supports Data Words to 10 Bits
• Clock Select Logic for Positive or Negative Edge
System Clocks
• Data Recirculate or Delay Modes of Operation
• Expandable Data Word Width or Buffer Length
• Three-State Outputs
• TTL Compatible Inputs/Outputs
• Low Power CMOS
Applications
• Sample Rate Conversion
• Data Time Compression/Expansion
• Software Controlled Data Alignment
• Programmable Serial Data Shifting
• Audio/Speech Data Processing Video/Image Processing
Video/Image Processing
• 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:
- High Resolution Monitor Delay Line
- Comb Filter Designs
- Progressive Scanning Display
- TV Standards Conversion
- Image Processing
Ordering Information
PART NUMBER
HSP9501JC-25
HSP9501JC-32
HSP9501JC-2596
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
PACKAGE
44 Ld PLCC
44 Ld PLCC
44 Ld PLCC
Tape and Reel
PKG.
NO.
N44.65
N44.65
N44.65
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
HSP9501
Pinout
44 LEAD PLCC
TOP VIEW
MODSEL
40
CLKSEL
CLK EN
LCEN
CLK
LC2
LC3
LC4
42
6
5
4
3
2
1
44
43
41
LC5
NC
NC
DO0
DO1
DO2
7
8
9
39 DI0
38 DI1
37 DI2
36 DI3
35 DI4
34 V
CC
33 GND
32 DI5
31 DI6
30 DI7
29 DI8
DO3 10
DO4 11
V
CC
12
GND 13
DO5 14
DO6 15
DO7 16
DO8 17
18
DO9
19
OE
20
LC0
21
LC1
22
LC10
23
LC9
24
LC8
25
LC7
26
LC6
27
DI9
DI 0 -9
10
10
10
28
NC
Block Diagram
MODSEL
REGISTER
MUX
CLKSEL
CLKEN
CLK
CLOCK
GENERATOR
REGISTER
11
LC0 -10
REGISTER
EN
11
PROGRAMMABLE
DELAY RAM
0-1279 DELAYS
10
REGISTER
10
LCEN
10
OE
10
DO0-9
3-2
HSP9501
Pin Descriptions
NAME
V
CC
GND
CLK
PIN NUMBER
12, 34
TYPE
DESCRIPTION
The +5V power supply pin. A 0.1µF capacitor between the V
CC
and GND pin is
recommended.
The device ground.
I
Input Clock. This clock signal is used to control the data movement through the programmable
buffer. It is also the signal which latches the input data, length control word and mode select. Input
setup and hold times with respect to the clock must be met for proper operation.
Data Inputs. This 10-bit input port is used to provide the input data. When MODSEL is low, data
on the DI0-9 inputs is latched on the clock edge selected by CLKSEL.
Data Outputs. This 10-bit port provides the output data from the Internal Delay Registers. Data
latched into the DI0-9 inputs will appear at the DO0 9 outputs on the Nth clock cycle, where N is
the total delay programmed.
Length Control Inputs. These inputs are used to specify the number of clock cycles of delay
between the DI0-9 inputs and the DO0-9 outputs. An integer value between 0 and 1279 is placed
on the LC0-10 inputs, and the total delay length (N) programmed is the LC0-10 value plus 2. In
order to properly load an active length control word, the value must be presented to the LC0-10
inputs and LCEN must be asserted during an active clock edge selected by CLKSEL.
Length Control Enable. LCEN is used in conjunction with LC0-10 and CLK to load a new length
control word. An 11-bit value is loaded on the LC0-10 inputs, LCEN is asserted, and the next
selected clock edge will load the new count value. Since this operation is synchronous, LCEN must
meet the specified setup/hold times with respect to CLK for proper operation.
Output Enable. This input controls the state of the DO0-9 output port. A low on this control line
enables the port for output. When OE is high, the output drivers are in the high impedance state.
Internal latching or transfer of data is not affected by this input.
Mode Select. This input is used to control the mode of operation of the HSP9501. A low on
MODSEL causes the device to latch new data at the DI0-9 inputs on every clock cycle, and operate
as a programmable pipeline register. When MODSEL is high, the HSP9501 is in the recirculate
mode, and will operate as a programmable length circular buffer. This control signal may be used
in a synchronous fashion during device operation, however, care must be taken to ensure the
required setup/hold times with respect to CLK are met.
Clock Select Control. This input is used to determine which edge of the CLK signal is used for
controlling all internal events. A low on CLKSEL selects the negative going edge, therefore, all
setup, hold, and output delay times are with respect to the negative edge of CLK. When CLKSEL
is high, the positive going edge is selected and all synchronous timing is with respect to the positive
edge of the CLK signal.
Clock Enable. This control signal can be used to enable or disable the CLK input. When low, the
CLK input is enabled and will operate in a normal fashion. A high on CLKEN will disable the CLK
input and will “hold'' all internal operations and data. This control signal may also be used in a
synchronous fashion, however, setup and hold requirements with respect to CLK must be met for
proper device operation. This signal takes effect on the clock following the one that latches it in.
13, 33
1
DIO-9
27, 29-32, 35-39
I
DO0-9
7-11, 14-18
O
LC0-10
20-26, 41-44
I
LCEN
6
I
OE
19
I
MODSEL
40
I
CLKSEL
5
I
CLKEN
2
I
3-3
HSP9501
Functional Description
The HSP9501 is a 10-bit wide programmable length data
buffer. The length of delay is programmable from 2 to 1281
delays in single delay increments.
Data into the delay line may be selected from the data input
bus (DI0-9) or as recirculated output, depending on the state
of the mode select (MODSEL) control input.
All synchronous timing (i.e., setup, hold and output
propagation delay times are relative to the CLK edge
selected by CLKSEL. Functional timing waveforms for each
state of CLKSEL are provided (refer to Timing Waveforms for
details).
Delay Path Control
The HSP9501 buffer length is programmable from 2 to 1281
data words in one word increments. The minimum number of
delays which can be programmed is two, consisting of the
input and Output Buffer Registers only.
The length control inputs (LC0-10) are used to set the length
of the programmable delay ram which can vary in length
from 0 to 1279. The total length of the HSP9501 data buffer
will then be equal to the programmed value on LC0-10 plus
2. The programmed delay is established by the 11-bit integer
value of the LC0-10 inputs with LC-10 as the MSB and LC0
as the LSB.
For example,
LC10
0
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
0
1
0
LC0
1
Mode Select
The MODSEL control pin selects the source of the data
moving into the delay line. When MODSEL is low, the data
input bus (DI0-9) is the source of the data. When MODSEL
is high, the output of the HSP9501 is routed back to the input
to form a circular buffer.
The MODSEL control line is latched at the input by the CLK
signal. The edge which latches this control signal is deter-
mined by the CLKSEL control line. In either case, the
MODSEL line is latched on one edge of the CLK signal with
the following edge moving data into and through the
HSP9501. Refer to the functional timing waveforms for
specific timing references.
Clock Select Logic
The clock select logic is provided to allow the use of positive
or negative edge system clocks. The active edge of the CLK
input to the HSP9501 is controlled through the use of the
CLKSEL input.
When CLKSEL is low, the negative going edge of CLK is
used to control all internal operations. A high on CLKSEL
selects the positive going edge of CLK.
programs a length value of 2
6
+ 2
0
= 65. The total length of
the delay will be 65 + 2 or 67 delays.
Table 1 indicates several programming values. The decimal
value placed on LC0-10 must not exceed 1279. Controlled
operation with larger values is not guaranteed.
Values on LC0-10 are latched on the CLK edge selected by
the CLKSEL control line, when LCEN is active. LC0-10 and
LCEN must meet the specified setup and hold times relative
to the selected CLK edge for proper device operation.
TABLE 1. LENGTH CONTROL PROGRAMMING EXAMPLES
TOTAL
LENGTH
N
2
120
810
1051
1281
LC10 2
10
0
0
0
1
1
LC9
2
9
0
0
1
0
0
LS8
2
8
0
0
1
0
0
LC7
2
7
0
0
0
0
1
LC6
2
6
0
1
0
0
1
LC5
2
5
0
1
1
0
1
LC4
2
4
0
1
0
1
1
LC3
2
3
0
0
1
1
1
LC2
2
2
0
1
0
0
1
LC1
2
1
0
1
0
0
1
LC0
2
0
0
0
0
1
1
PROGRAMMED
LENGTH
0
118
808
1049
1279
3-4
HSP9501
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or Voltage Applied . . . . . . . .GND -0.5V to V
CC
+0.5V
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45.2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(PLCC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to 5.25V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
Standby Current
Operating Power Supply Current
V
CC
= 5.0V +5%, T
A
= 0
o
C to 70
o
C, Commercial
SYMBOL
V
IH
V
IL
V
OH
V
OL
I
I
I
O
I
CCSB
I
CCOP
C
IN
C
O
TEST CONDITIONS
V
CC
= 5.25V
V
CC
= 4.75V
I
OH
= -4mA V
CC
= 4.75V
I
OL
= +4.0mA V
CC
= 4.75V
V
IN
= GND or V
CC
V
CC
= 5.25V
V
OUT
= GND or V
CC
= 5.25V
V
IN
= V
CC
or GND, V
CC
= 5.25V, Note 3
f = 25MHz, V
IN
= V
CC
or GND
V
CC
= 5.25V, Notes 2, 3
FREQ = 1MHz, V
CC
= Open, All
measurements are referenced to device
GND
MIN
2.0
-
2.4
-
-10
-10
-
-
MAX
-
0.8
-
0.4
10
10
500
125
UNITS
V
V
V
V
µA
µA
µA
mA
Input Capacitance
Output Capacitance
-
-
10
10
pF
pF
AC Electrical Specifications
V
CC
= 5.0V
±5%,
T
A
= 0
o
C to +70
o
C, Commercial, (Note 5)
-32
-25
MAX
-
-
-
-
-
20
24
-
-
-
-
-
MIN
40
15
-
12
2
-
-
12
2
13
2
13
MAX
-
-
15
-
-
25
25
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
-
-
-
-
-
-
Note 4
-
-
-
-
-
PARAMETER
Clock Period
Clock Pulse Width High
Clock Pulse Width Low
Data Input Setup Time
Data Input Hold Time
Output Enable Time
Output Disable Time
CLKEN to Clock Setup
CLKEN to Clock Hold
LC0-10 Setup Time
LC0-10 Hold Time
LCEN to Clock Setup
SYMBOL
t
CP
t
PWH
t
PWL
t
DS
t
DH
t
ENA
t
DIS
t
ES
t
EH
t
LS
t
LH
t
LES
MIN
31
12
12
10
2
-
-
10
2
10
2
10
3-5
FPGA/CPLD
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