Datasheet> 器件分类 > 存储> 存储> AS7C331MPFS18A-166TQCN

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AS7C331MPFS18A-166TQCN: 产品描述3.3V 1M x 18 pipelined burst synchronous SRAM; 产品类别存储存储; 文件大小490KB，共19页; 制造商ALSC [Alliance Semiconductor Corporation]; 标准

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AS7C331MPFS18A-166TQCN概述

3.3V 1M x 18 pipelined burst synchronous SRAM

AS7C331MPFS18A-166TQCN规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	ALSC [Alliance Semiconductor Corporation]
零件包装代码	QFP
包装说明	LQFP, QFP100,.63X.87
针数	100
Reach Compliance Code	unknow
ECCN代码	3A991.B.2.A
最长访问时间	3.4 ns
其他特性	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	166 MHz
I/O 类型	COMMON
JESD-30 代码	R-PQFP-G100
JESD-609代码	e3
长度	20 mm
内存密度	18874368 bi
内存集成电路类型	STANDARD SRAM
内存宽度	18
功能数量	1
端子数量	100
字数	1048576 words
字数代码	1000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	1MX18
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LQFP
封装等效代码	QFP100,.63X.87
封装形状	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	245
电源	2.5/3.3,3.3 V
认证状态	Not Qualified
座面最大高度	1.6 mm
最大待机电流	0.04 A
最小待机电流	3.14 V
最大压摆率	0.29 mA
最大供电电压 (Vsup)	3.465 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	MATTE TIN
端子形式	GULL WING
端子节距	0.65 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	14 mm

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December 2004

AS7C331MPFS18A

3.3V 1M x 18 pipelined burst synchronous SRAM

Features

•

Organization: 1,048,576 x18 bits

Fast clock speeds to 166MHz

Fast clock to data access: 3.4/3.8 ns

Fast OE access time: 3.4/3.8 ns

Fully synchronous register-to-register operation

Single-cycle deselect

Asynchronous output enable control

Available 100-pin TQFP package

•

Individual byte write and global write

Multiple chip enables for easy expansion

3.3 V core power supply

2.5 V or 3.3V I/O operation with separate V

DDQ

Linear or interleaved burst control

Common data inputs and data outputs

Snooze mode for reduced power-standby

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[19:0]

CLK

CLR

Burst logic

Address

18 20

1M x 18

Memory

array

CLK

GWE

BWE

CE0

CE1

CE2

DQb

CLK

DQa

Byte Write

registers

Byte Write

registers

CLK

Enable

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

DQ[a,b]

Selection guide

-166

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

166

3.4

290

-133

7.5

133

3.8

270

Units

MHz

12/23/04, v 2.6

Alliance Semiconductor

1 of 19

AS7C331MPFS18A

Functional description

The AS7C331MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device

organized as 1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any

given technology.

Fast cycle times of 6/7.5 ns with clock access times (t

) of 3.4/3.8 ns enable 166, and 133 MHz bus frequencies. Three chip

enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address

strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated

burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In

a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK is

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for the

next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO

input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the

device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes

may be written by asserting BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low.

Address is incremented internally to the next burst address if BWn and ADV are sampled low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP are as follows:

• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C331MPFS18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at

2.5V or 3.3V. These devices are available in a 100-pin TQFP package.

TQFP capacitance

Parameter

Input capacitance

I/O capacitance

* Guaranteed not tested

Symbol

IN*

I/O*

Test conditions

= 0V

OUT

= 0V

Min

Max

Unit

TQFP thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer

4–layer

Symbol

Typical

Units

°C/W

12/23/04, v 2.6

Alliance Semiconductor

4 of 19

AS7C331MPFS18A-166TQCN相似产品对比

	AS7C331MPFS18A-166TQCN	AS7C331MPFS18A-166TQIN	AS7C331MPFS18A-166TQI	AS7C331MPFS18A-133TQIN	AS7C331MPFS18A-133TQI	AS7C331MPFS18A-166TQC	AS7C331MPFS18A-133TQC	AS7C331MPFS18A
描述	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM	3.3V 1M x 18 pipelined burst synchronous SRAM
是否Rohs认证	符合	符合	不符合	符合	不符合	不符合	不符合	-
厂商名称	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	-
零件包装代码	QFP	QFP	QFP	QFP	QFP	QFP	QFP	-
包装说明	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	-
针数	100	100	100	100	100	100	100	-
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow	unknow	unknow	-
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	-
最长访问时间	3.4 ns	3.4 ns	3.4 ns	3.8 ns	3.8 ns	3.4 ns	3.8 ns	-
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-
最大时钟频率 (fCLK)	166 MHz	166 MHz	166 MHz	133 MHz	133 MHz	166 MHz	133 MHz	-
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	-
JESD-30 代码	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	-
JESD-609代码	e3	e3	e0	e3	e0	e0	e0	-
长度	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	-
内存密度	18874368 bi	18874368 bi	18874368 bi	18874368 bi	18874368 bi	18874368 bi	18874368 bi	-
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	-
内存宽度	18	18	18	18	18	18	18	-
功能数量	1	1	1	1	1	1	1	-
端子数量	100	100	100	100	100	100	100	-
字数	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	-
字数代码	1000000	1000000	1000000	1000000	1000000	1000000	1000000	-
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-
最高工作温度	70 °C	85 °C	85 °C	85 °C	85 °C	70 °C	70 °C	-
组织	1MX18	1MX18	1MX18	1MX18	1MX18	1MX18	1MX18	-
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	-
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
封装代码	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	-
封装等效代码	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	-
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
封装形式	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	-
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-
峰值回流温度（摄氏度）	245	245	NOT SPECIFIED	245	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
电源	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	-
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	-
最大待机电流	0.04 A	0.04 A	0.04 A	0.04 A	0.04 A	0.04 A	0.04 A	-
最小待机电流	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	-
最大压摆率	0.29 mA	0.29 mA	0.29 mA	0.27 mA	0.27 mA	0.29 mA	0.27 mA	-
最大供电电压 (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	-
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	-
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-
表面贴装	YES	YES	YES	YES	YES	YES	YES	-
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	-
温度等级	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	-
端子面层	MATTE TIN	MATTE TIN	Tin/Lead (Sn/Pb)	MATTE TIN	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	-
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	-
处于峰值回流温度下的最长时间	30	30	NOT SPECIFIED	30	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	-

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