Programmable FemtoClock
®
NG LVPECL/LVDS
Dual 4-Output Fractional Clock Generator
IDT8T49N524I
DATA SHEET
General Description
The IDT8T49N524I is an eight output programmable any-rate dual
clock generator with selectable LVDS or LVPECL outputs. Both clock
generators use Fractional Output Dividers to be able to generate out-
put frequencies that are independent of each other and independent
of the input frequency. Output frequencies for both clock generators
are generated from a single crystal or reference clock.
Clock Generator A supports three different factory-programmed
default frequencies that can be selected from using only the FSEL
control pins. Alternatively any desired output frequency can be
programmed over the I
2
C serial port. The chosen output frequency is
then driven out the QA0 to QA3 outputs.
Clock Generator B supports a single factory-programmed default
frequency. It can also be programmed for any output frequency via
the serial port. The output frequency is driven out the QB0 to QB3
outputs.
Some examples of frequency configurations that can be achieved
are shown in Table 5A. Please consult IDT for programming software
that can be used to determine the required settings for any desired
configuration.
Excellent phase noise performance is achieved with IDT’s fourth
Generation FemtoClock
®
NG PLL technology, which delivers
sub-0.5ps RMS phase jitter in the integer divide mode.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock
®
NG PLL technology
Eight outputs selectable as LVPECL or LVDS
Input selectable: fundamental mode crystal or clock reference
Supports fundamental mode crystals from 10MHz - 40MHz
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
Input frequencies from 5MHz up to 800MHz
Two independent output frequencies can be generated
Output frequencies independent of each other and of input
Output frequencies from 15.234MHz - 645MHz, and
975MHz - 1290MHz, (See Table 5D for details)
RMS phase jitter at 125MHz (12kHz - 20MHz): 0.282ps (typical)
RMS phase jitter at 156.25MHz (12kHz - 20MHz):
0.278ps (typical)
Full 2.5V or 3.3V power supply
I
2
C programming interface
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V (LVPECL only)
2.5V / 2.5V / 2.5V
Pin Assignment
V
CCO_B
nQB1
nQB0
nQB2
nQB3
QB0
V
EE_B
QB1
QB2
QB3
V
EE_B
30
29 28 27 26 25 24 23 22 21
31
20
32
33
34
35
36
37
38
39
40
1 2
nQA0
QA0
FSEL1
V
CC
V
EE
ADDR_SEL
FSEL0
nCLK
CLK
V
EE
SCLK
SDATA
V
EE
IDT8T49N524I
19
18
V
CCA
LOCK
V
EE
V
CC
CLK_SEL
V
EE_A
40 Lead VFQFN
17
6mm x 6mm x 0.925mm
16
4.65mm x 4.65mm EPad
15
NL Package
14
Top View
3
4
nQA1
QA1
13
12
11
8
QA3
XTAL_OUT
XTAL_IN
5 6
QA2
7
nQA2
9
10
nQA3
V
EE_A
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
1
V
CCO_A
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Block Diagram
LOCK
QA0
nQA0
CLK SEL
Pulldown
÷NINT_1[5:0]
÷2
÷NFRAC_1[15:0]
0
QA1
nQA1
QA2
XTAL_IN
XTAL_OUT
CLK
nCLK
Pulldown
PU/PD
Xtal
Osc
÷2
0
x2
÷P[1:0]
1
Phase
Detector
+
Charge
Pump
1
FemtoClock
®
NG
VCO
1
nQA2
QA3
nQA3
0
QB0
÷2
÷NINT_2[5:0]
1
nQB0
QB1
÷MINT [8:1]
÷ NFRAC_2[15:0]
FSEL0
FSEL1
SCLK
SDATA
ADDR_SEL
Pulldown
Pulldown
Pullup
Pullup
Pulldown
÷2
0
nQB1
QB2
nQB2
Divider,
Output Type
&
Output
Enable
Selection
QB3
OUTPUT ENABLE
OUTPUT STYLE
8
nQB3
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
2
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Pin Description & Characteristics
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6, 7
8, 9
10, 13, 18,
21, 31, 34,
37, 40
11,
12
14
15
16,
20
17
19, 38
22, 23
24, 25
26
27, 28
29, 30
32
33
35
36
39
Name
QA0, nQA0
QA1, nQA1
V
CCO_A
QA2, nQA2
QA3, nQA3
V
EE
XTAL_IN
XTAL_OUT
CLK
nCLK
FSEL0,
FSEL1
ADDR_SEL
V
CC
nQB3, QB3
nQB2, QB2
V
CCO_B
nQB1, QB1
nQB0, QB0
SCLK
SDATA
V
CCA
LOCK
CLK_SEL
Output
Output
Power
Output
Output
Power
Type
Description
Clock generator A differential output pair. LVPECL or LVDS interface levels.
Clock generator A differential output pair. LVPECL or LVDS interface levels.
Clock generator A output supply pin.
Clock generator A differential output pair. LVPECL or LVDS interface levels.
Clock generator A differential output pair. LVPECL or LVDS interface levels.
Negative supply pins.
Input
Input
Input
Input
Input
Power
Output
Output
Power
Output
Output
Input
Input/Output
Power
Output
Input
Pulldown
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
CC
/2.
Frequency select pins. See Table 4A for frequency selection.
LVCMOS/LVTTL interface levels.
I
2
C Address select pin. LVCMOS/LVTTL interface levels.
Core supply pins.
Clock generator B differential output pair. LVPECL or LVDS interface levels.
Clock generator B differential output pair. LVPECL or LVDS interface levels.
Clock generator B output supply pin.
Clock generator B differential output pair. LVPECL or LVDS interface levels.
Clock generator B differential output pair. LVPECL or LVDS interface levels.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
I
2
C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open
Drain.
Analog supply pin.
PLL Lock Indicator.
Input source control pin. LVCMOS/LVTTL interface levels.
0 = Crystal is input source (default)
1 = CLK, nCLK input reference clock is input source
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
3
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Register Map
Table 3. I
2
C Register Map
Binary
Register
Register Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
Register Bit
D7
MINT0[7]
MINT1[7]
MINT2[7]
reserved
unused
unused
NFRACB[7]
NFRACB[15]
NINTA_0[5]
NINTA_1[5]
NINTA_2[5]
reserved
OE_QB3
unused
1
unused
D6
MINT0[6]
MINT1[6]
MINT2[6]
reserved
unused
unused
NFRACB[6]
NFRACB[14]
NINTA_0[4]
NINTA_1[4]
NINTA_2[4]
reserved
OE_QB2
unused
1
unused
D5
MINT0[5]
MINT1[5]
MINT2[5]
reserved
NINTB[5]
unused
NFRACB[5]
NFRACB[13]
NINTA_0[3]
NINTA_1[3]
NINTA_2[3]
reserved
OE_QB1
unused
DOUBLER_
ENABLE
1
D4
MINT0[4]
MINT1[4]
MINT2[4]
reserved
NINTB[4]
unused
NFRACB[4]
NFRACB[12]
NINTA_0[2]
NINTA_1[2]
NINTA_2[2]
reserved
OE_QB0
unused
unused
1
D3
MINT0[3]
MINT1[3]
MINT2[3]
reserved
NINTB[3]
unused
NFRACB[3]
NFRACB[11]
NINTA_0[1]
NINTA_1[1]
NINTA_2[1]
reserved
OE_QA3
LVDS_SEL
unused
D2
MINT0[2]
MINT1[2]
MINT2[2]
reserved
NINTB[2]
unused
NFRACB[2]
NFRACB[10]
NINTA_0[0]
NINTA_1[0]
NINTA_2[0]
reserved
OE_QA2
PLL_BYPASS
unused
D1
MINT0[1]
MINT1[1]
MINT2[1]
reserved
NINTB[1]
DIVB_BYPASS
NFRACB[1]
NFRACB[9]
CP0[1]
CP1[1]
CP2[1]
reserved
OE_QA1
P[1]
DIVA_BYPASS
D0
MINT0[0]
MINT1[0]
MINT2[0]
reserved
NINTB[0]
DIVB_INT
NFRACB[0]
NFRACB[8]
CP0[0]
CP1[0]
CP2[0]
reserved
OE_QA0
P[0]
DIVA_INT
1
NFRACA_0[8]
NFRACA_1[8]
NFRACA_2[8]
reserved
NFRACA_0[0]
NFRACA_1[0]
NFRACA_2[0]
reserved
1
1
1
NFRACA_0[9]
NFRACA_1[9]
NFRACA_2[9]
reserved
NFRACA_0[1]
NFRACA_1[1]
NFRACA_2[1]
reserved
NFRACA_0[15] NFRACA_0[14] NFRACA_0[13] NFRACA_0[12] NFRACA_0[11] NFRACA_0[10]
NFRACA_1[15] NFRACA_1[14] NFRACA_1[13] NFRACA_1[12] NFRACA_1[11] NFRACA_1[10]
NFRACA_2[15] NFRACA_2[14] NFRACA_2[13] NFRACA_2[12] NFRACA_2[11] NFRACA_2[10]
reserved
NFRACA_0[7]
NFRACA_1[7]
NFRACA_2[7]
reserved
reserved
NFRACA_0[6]
NFRACA_1[6]
NFRACA_2[6]
reserved
reserved
NFRACA_0[5]
NFRACA_1[5]
NFRACA_2[5]
reserved
reserved
NFRACA_0[4]
NFRACA_1[4]
NFRACA_2[4]
reserved
reserved
NFRACA_0[3]
NFRACA_1[3]
NFRACA_2[3]
reserved
reserved
NFRACA_0[2]
NFRACA_1[2]
NFRACA_2[2]
reserved
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
4
©2014 Integrated Device Technology, Inc.
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Function Tables
Table 4A. Frequency Select Table
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Pre-scaler
Ratio
P
P
P
Feedback
Divider Ratio
MINT0
MINT1
MINT2
QAn Operation
NINTA_0
NINTA_1
NINTA_2
Reserved
NFRACA_0
NFRACA_1
NFRACA_2
QBn Operation
NINTB
NINTB
NINTB
NFRACB
NFRACB
NFRACB
Table 4B. I
2
C Register Function Descriptions
Bits
MINTn[7:0]
P[1:0]
NINTA_n[5:0]
NFRACA_n[15:0]
NINTB[5:0]
NFRACB[15:0]
CPn[1:0]
Name
Integer Feedback Divider Register n
(n = 0...2)
Input Divider Register
Output Divider A - Integer Portion n
(n = 0...2)
Output Divider A - Fractional Portion
(n = 0...2)
Output Divider B - Integer Portion
Output Divider B - Fractional Portion
PLL Bandwidth n (n = 0...2)
Function
Sets the integer feedback divider value. See Table 5B for the feedback
divider coding.
Sets the PLL input divider. The divider value has the range of 1, 2, 4 and
8. See Table 5C for the divider coding.
Sets the integer portion of the output divider A. See Table 5D for the
output divider coding.
Sets the fractional portion of the output divider A. See Table 5D for the
output divider coding.
Sets the integer portion of the output divider B. See Table 5D for the
output divider coding.
Sets the fractional portion of the output divider B. See Table 5D for the
output divider coding.
Sets the FemtoClock
®
NG PLL Charge Pump current to support the
selected operating frequency. See Table 5E.
Sets the desired output to Active or High impedance.
0 = Output is high-impedance (default)
1 = Output is active.
Selects differential output style
0 = LVPECL (default)
1 = LVDS
Bypasses PLL. Input to phase detector is routed through output dividers
A and B to the output fanout buffers. Dividers should be programmed for
integer divide operation (DIVA_INT = DIVB_INT = 0) for proper operation.
Enables the input frequency doubler.
0 = Input frequency presented directly to PLL
1 = Input frequency doubled before PLL (default)
Bypasses output divider A. QAn output frequency is VCO/2.
Bypasses output divider B. QBn output frequency is VCO/2.
Disables fractional portion of divider A. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
Disables fractional portion of divider B. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
OE_Qxx
Output Enable
LVDS_SEL
Output Style
PLL_BYPASS
PLL Bypass
DOUBLER_
ENABLE
DIVA_BYPASS
DIVB_BYPASS
DIVA_INT
DIVB_INT
Input Doubler
Bypass Output Divider A
Bypass Output Divider B
Divider A Integer Mode
Divider B Integer Mode
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
5
©2014 Integrated Device Technology, Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
