NXP Semiconductors
Data Sheet: Technical Data
K26P169M180SF5
Rev. 4, 04/2017
Kinetis K26 Sub-Family
180 MHz ARM® Cortex®-M4F Microcontroller.
MK26FN2M0VMD18
MK26FN2M0VMI18
MK26FN2M0VLQ18
MK26FN2M0CAC18R
The K26 sub-family members provide greater performance,
memory options up to 2 MB total flash and 256 KB of SRAM, as
well as higher peripheral integration with features such as Dual
USB. These devices maintain hardware and software
compatibility with the existing Kinetis family.
This product also offers:
• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run
mode
• Smarter peripherals with operation in Stop modes
144 MAPBGA (MD)
144 LQFP (LQ)
13 mm x 13 mm Pitch 1 20 mm x 20 mm Pitch
mm
0.5 mm
169 MAPBGA (MI)
9 mm x 9 mm Pitch
0.65 mm
169 WLCSP (AC)
5.6 mm x 5.5 mm Pitch
0.4 mm
Performance
• Up to 180 MHz ARM Cortex-M4 based core with DSP
instructions and Single Precision Floating Point unit
System and Clocks
• Multiple low-power modes to provide power
optimization based on application requirements
• Memory protection unit with multi-master protection
Memories and memory expansion
• 3 to 32 MHz main crystal oscillator
• Up to 2 MB program flash memory on non-FlexMemory
• 32 kHz low power crystal oscillator
devices with 256 KB RAM
• 48 MHz internal reference
• Up to 1 MB program flash memory and 256 KB of
Security
FlexNVM on FlexMemory devices
• 4 KB FlexRAM on FlexMemory devices
• Hardware random-number generator
• FlexBus external bus interface and SDRAM controller
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
Analog modules
Timers
• Two 16-bit SAR ADCs and two 12-bit DAC
• Four analog comparators (CMP) containing a 6-bit
• Four Periodic interrupt timers
DAC and programmable reference input
• 16-bit low-power timer
• Voltage reference 1.2V
• Two 16-bit low-power timer PWM modules
• Two 8-channel motor control/general purpose/PWM
Communication interfaces
timers
• USB high-/full-/low-speed On-the-Go with on-chip high
• Two 2-ch quad decoder/general purpose timers
speed transceiver
• Real-time clock
• USB full-/low-speed OTG with on-chip transceiver
Operating Characteristics
• Two CAN, three SPI and four I2C modules
• Low Power Universal Asynchronous Receiver/
• Voltage/Flash write voltage range:1.71 to 3.6 V
Transmitter 0 (LPUART0) and five standard UARTs
• V-Temperature range (ambient): -40 to 105°C
• Secure Digital Host Controller (SDHC)
• C-Temperature range (ambient): -40 to 85°C
• I2S module
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
1
Part Number
Flash
MK26FN2M0VMD18
MK26FN2M0VLQ18
MK26FN2M0CAC18R
MK26FN2M0VMI18
2 MB
2 MB
2 MB
2 MB
Memory
SRAM
256 KB
256 KB
256 KB
256 KB
100
100
116
116
Maximum number of I\O's
1. To confirm current availability of orderable part numbers, go to
http://www.nxp.com
and perform a part number search.
Related Resources
Type
Selector
Guide
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
Resource
Solution Advisor
K26P169M180SF5RM
This document.
The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N
1
a particular device mask set.
Package dimensions are provided in package drawings.
MAPBGA 144-pin :
98ASA00222D
1
QFP 144-pin: 98ASS23177W
1
MAPBGA 169-pin :
98ASA00628D
1
WLCSP 169-pin:
98ASA00222D
1
1. To find the associated resource, go to
http://www.nxp.com
and perform a search using this term.
2
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Kinetis K26 Sub-Family
ARM
®
Cortex
®
-M4
Core
System
Internal
and external
watchdogs
Debug
interfaces
Interrupt
controller
DSP
Memory
protection
Memories and Memory Interfaces
Program
flash
Clocks
Phase-
locked loop
Frequency-
locked loop
Low/high
frequency
oscillators
RAM
FlexMemory
Serial
programming
interface
SDRAM
controller
Cache
Floating-
point unit
DMA
External
bus
Low-leakage
wakeup
Internal
reference
clocks
and Integrity
CRC
Random
number
generator
Hardware
encryption
Security
Analog
16-bit ADC
x2
Timers
Timers
x4 (20ch)
Communication Interfaces
I
C
x4
UART
x5
SPI
x3
CAN
x2
2
Human-Machine
Interface (HMI)
GPIO
Xtrinsic
touch-sensing
interface
I
S
x1
Secure
Digital
USB LS/FS
OTG
controller
with
transceiver
2
Analog
comparator
x4
6-bit DAC
x4
12-bit DAC
x2
Carrier
modulator
transmitter
Programmable
delay block
Periodic
interrupt
timers
Low power
timer
Voltage
reference
LPUART
Independent
real-time
clock
Low power
TPM x 2 (4ch)
USB LS/FS/HS
OTG
controller
with
transceiver
USB DCD/
USBHSDCD
USB voltage
regulator
Figure 1. K26 Block Diagram
Kinetis K26 Sub-Family, Rev. 4, 04/2017
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 6
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1
Voltage and current operating requirements.....7
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 9
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 12
2.2.6
EMC radiated emissions operating behaviors...17
2.2.7
Designing with radiated emissions in mind....... 18
2.2.8
Capacitance attributes...................................... 18
2.3 Switching specifications...................................................18
2.3.1
Device clock specifications............................... 18
2.3.2
General switching specifications....................... 19
2.4 Thermal specifications..................................................... 20
2.4.1
Thermal operating requirements....................... 20
2.4.2
Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 22
3.1 Core modules.................................................................. 22
3.1.1
Debug trace timing specifications..................... 22
3.1.2
JTAG electricals................................................ 23
3.2 System modules.............................................................. 26
3.3 Clock modules................................................................. 26
3.3.1
MCG specifications........................................... 26
3.3.2
IRC48M specifications...................................... 29
3.3.3
Oscillator electrical specifications..................... 30
3.3.4
32 kHz oscillator electrical characteristics.........32
3.4 Memories and memory interfaces................................... 33
3.4.1
Flash (FTFE) electrical specifications............... 33
3.4.2
EzPort switching specifications......................... 38
3.4.3
Flexbus switching specifications....................... 38
3.4.4
SDRAM controller specifications.......................41
3.5 Analog............................................................................. 44
3.5.1
ADC electrical specifications.............................44
3.5.2
CMP and 6-bit DAC electrical specifications.....48
3.5.3
12-bit DAC electrical characteristics................. 51
3.5.4
Voltage reference electrical specifications........ 54
3.6 Timers..............................................................................55
3.7 Communication interfaces............................................... 55
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
USB Voltage Regulator Electrical
Specifications.................................................... 56
USB Full Speed Transceiver and High Speed
PHY specifications............................................ 57
USB DCD electrical specifications.................... 57
CAN switching specifications............................ 58
DSPI switching specifications (limited voltage
range)................................................................58
DSPI switching specifications (full voltage
range)................................................................60
3.7.7
Inter-Integrated Circuit Interface (I2C) timing....61
3.7.8
UART switching specifications.......................... 63
3.7.9
Low Power UART switching specifications....... 63
3.7.10 SDHC specifications......................................... 63
3.7.11 I2S switching specifications.............................. 65
3.8 Human-machine interfaces (HMI)....................................71
3.8.1
TSI electrical specifications...............................71
4 Dimensions............................................................................. 71
4.1 Obtaining package dimensions....................................... 71
5 Pinout...................................................................................... 72
5.1 MK26 Signal Multiplexing and Pin Assignments..............72
5.2 Recommended connection for unused analog and
digital pins........................................................................81
5.3 MK26 Pinouts.................................................................. 82
6 Ordering parts......................................................................... 86
6.1 Determining valid orderable parts....................................86
7 Part identification.....................................................................87
7.1 Description.......................................................................87
7.2 Format............................................................................. 87
7.3 Fields............................................................................... 87
7.4 Example...........................................................................88
8 Terminology and guidelines.................................................... 88
8.1 Definitions........................................................................ 88
8.2 Examples......................................................................... 89
8.3 Typical-value conditions.................................................. 89
8.4 Relationship between ratings and operating
requirements....................................................................90
8.5 Guidelines for ratings and operating requirements..........90
9 Revision History...................................................................... 90
4
NXP Semiconductors
Kinetis K26 Sub-Family, Rev. 4, 04/2017
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
T
STG
T
SDR
Description
Storage temperature
Solder temperature, lead-free
Min.
–55
—
Max.
150
260
Unit
°C
°C
Notes
1
2
1. Determined according to JEDEC Standard JESD22-A103,
High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
—
Max.
• For C-
temp
varian
t: 1
• For V-
temp
varian
t :3
Unit
—
Notes
1
1. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
V
HBM
V
CDM
I
LAT
Description
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device
model
Latch-up current at ambient temperature of 105°C
Min.
-2000
-500
-100
Max.
+2000
+500
+100
Unit
V
V
mA
Notes
1
2
3
1. Determined according to JEDEC Standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101,
Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78,
IC Latch-Up Test.
Kinetis K26 Sub-Family, Rev. 4, 04/2017
5
NXP Semiconductors
NXP MCU
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