HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
Features
◆
IDT71V30S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial 35ns (max.)
Low-power operation
– IDT71V30S
—
Active: 375mW (typ.)
—
Standby: 5mW (typ.)
– IDT71V30L
—
Active: 375mW (typ.)
—
Standby: 1mW (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
On-chip port arbitration logic
Interrupt flags for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation, 2V data retention (L Only)
TTL-compatible, single 3.3V ±0.3V power supply
Industrial temperature range (-40
O
C to +85
O
C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/
W
L
OE
R
CE
R
R/
W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
(1)
A
9L
A
0L
Address
Decoder
10
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
3741 drw 01
(2)
NOTES:
1. IDT71V30:
BUSY
outputs are non-tristatable push-pulls.
2.
INT
outputs are non-tristable push-pull output structure.
DECEMBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC 3741/13
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71V30 is a high-speed 1K x 8 Dual-Port Static RAM. The
IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port
SRAM.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by
CE,
permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 375mW of power. Low-power (L) ver-
sions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71V30 devices are packaged in 64-pin STQFPs.
Pin Configurations
(1,2,3)
N/C
N/C
N/C
INT
L
BUSY
L
R/W
L
CE
L
V
CC
V
CC
CE
R
R/W
R
BUSY
R
INT
R
N/C
N/C
N/C
INDEX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IDT71V30TF
PP64
(4)
64-Pin STQFP
Top View
(5)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
3741 drw 03
NOTES:
1. All V
CC
pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking.
I/O
3L
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
N/C
I/O
4R
I/O
5R
6.42
2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
BIAS
T
STG
T
JN
(3)
Rating
Terminal Voltage
with Respect to GND
Temperature
Under Bias
Storage
Temperature
Junction Temperature
DC Output
Current
Com'l & Ind
-0.5 to +4.60
-55 to +125
-65 to +150
+150
50
Unit
V
o
Recommended
DC Operating Conditions
Symbol
V
CC
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
CC
+
0.3V
0.8
Unit
V
V
V
V
3741 tbl 02
C
C
C
GND
V
IH
V
IL
o
o
I
OUT
mA
NOTE:
1. V
IL
(min.) = -1.5V for pulse width less than 20ns.
3741 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
3. This is the absolute maximum junction temperature for the device. No DC Bias.
Maximum Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3
3.3V
+
0.3
3741 tbl 03
Capacitance
(1)
(T
A
= +25
O
C,
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
Output Capacitance
V
IN
= 3dV
f=1.0MHz)
Max.
9
10
Unit
pF
pF
3741 tbl 04
Conditions
(2)
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers,
contact your sales office.
V
OUT
= 3dV
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
NOTE:
(V
CC
= 3.3V ± 0.3V)
71V30L
Min.
___
71V30S
Parameter
Input Leakage
Current
(1)
Output Leakage
Current
Output Low Voltage
(I/O
0
-I/O
7
)
Output High Voltage
Test Conditions
V
CC
= 3.6V,
V
IN
= 0V to V
CC
CE
= V
IH
,
V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3741 tbl 05
___
___
___
___
2.4
2.4
1. At Vcc < 2.0V input leakages are undefined.
Supply CurrentV
IN
> V
CC
-0.2V or < 0.2V
3
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6,7)
(V
CC
= 3.3V ± 0.3V)
71V30X25
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(2)
75
75
___
___
71V30X35
Com'l & Ind
Typ.
(2)
75
75
___
71V30X55
Com'l Only
Typ.
(2)
75
75
___
___
Max.
150
120
___
___
Max.
145
115
___
Max.
135
105
___
___
Unit
mA
75
20
20
___
145
50
35
___
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
and
CE
R
= V
IL
,
f = f
MAX
(3)
20
20
___
___
50
35
___
___
20
20
___
___
50
35
___
___
mA
20
30
30
___
50
100
70
___
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
30
30
___
___
105
75
___
___
30
30
___
___
90
60
___
___
mA
30
1.0
0.2
___
100
5.0
3.0
___
I
SB3
Full Standby Current (Both CE
L
and CE
R
> V
CC
- 0.2V
Ports - CMOS Level Inputs) V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
1.0
0.2
___
___
5.0
3.0
___
___
1.0
0.2
___
___
5.0
3.0
___
___
mA
1.0
30
30
___
5.0
85
70
___
I
SB4
Full Standby Current
(One Port - CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f=f
MAX
(3)
30
30
___
___
90
75
___
___
30
30
___
___
75
60
___
___
mA
30
85
3741 tbl 06
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. V
CC
= 3.3V, T
A
= +25°C, and are not production tested. I
CCDC
= 70mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to chip enable Truth Table I.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics
Symbol
V
DR
I
CCDR
Parameter
V
CC
for Data Retention
Data Retention Current
(L Version Only)
71V30L
Test Condition
Min.
2.0
Ind.
____
____
Typ.
(1)
____
Max.
____
Unit
V
µA
100
100
____
____
1000
500
____
____
V
CC
= 2
V,
CE
> V
CC
-0.2V
t
CDR
(3)
t
R
(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
V
IN
> V
CC
-0.2V or V
IN
< 0.2V
Com'l.
0
t
RC
(2)
ns
ns
3741 tbl 07
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and is not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
4
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
3741 tbl 08
Data Retention Waveform
DATA RETENTION MODE
V
DR
≥
2.0V
V
CC
3.0V
t
CDR
3.0V
t
R
CE
V
IH
V
DR
V
IH
3741 drw 04
,
3.3V
590Ω
DATA
OUT
BUSY
INT
435Ω
DATA
OUT
30pF
435Ω
3.3V
590Ω
5pF
3741 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For t
HZ
, t
LZ
, t
WZ
and t
OW
)
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(3,4)
71V30X25
Com'l Only
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
25
____
____
____
____
71V30X35
Com'l & Ind
Min.
Max.
71V30X55
Com'l Only
Min.
Max.
Unit
Parameter
Min.
Max.
35
____
____
____
____
55
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
3741 tbl 09
25
25
12
____
____
35
35
20
____
____
55
55
25
____
____
3
0
____
3
0
____
3
0
____
12
____
15
____
30
____
0
____
0
____
0
____
50
50
50
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and power contact your sales office.
5
6.42
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
