Low Skew, 1-to-12 (IDCS)
LVCMOS/LVTTL Clock Generator
Datasheet
879893
General Description
The 879893 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two LVCMOS/LVTTL
clock signals from which it generates 12 new LVCMOS/LVTTL
clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.
The 879893 Intelligent Dynamic Clock Switch (IDCS) circuit
continuously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
nALARM for that CLK will be latched (LOW). If that CLK is the
primary clock, the IDCS will switch to the good secondary clock
and phase/frequency alignment will occur with minimal output
phase disturbance.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Twelve LVCMOS/LVTTL outputs (two banks of six outputs);
One QFB feedback clock output
Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
Automatically detects clock failure
IDCS on-chip intelligent dynamic clock switch
Maximum output frequency: 200MHz
Output skew: 50ps (maximum), within bank
Cycle-to-cycle (FSEL3=0, V
DD
=3.3V±5%): 150ps (maximum)
Smooth output phase transition during clock fail-over switch
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement part use 87973i
Simplified Block Diagram
nOE/MR
Pulldown
Pin Assignment
V
DD
nALARM_RST
REF_SEL
nPLL_EN
GND
FSEL0
FSEL1
GND
FSEL2
FSEL3
nOE/MR
6
D
Q
FSEL0 FSEL1 FSEL2 QA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷2
÷2
÷2
÷4
÷2
÷16
÷8
÷4
CLK0
CLK1
FB
REF_SEL
nMAN/A
nALARM_RST
nPLL_EN
Pulldown
Pulldown
0
REF
1
1
PLL
VCO R
ANGE
240MHz - 500MHz
FB
0
QA0:QA5
GND
QA0
QA1
V
DD
GND
QA2
QA3
V
DD
GND
QA4
QA5
V
DD
Pulldown
Pullup
Pullup
IDCS
÷2
0
D
1
Q
6
QB0:QB5
Pulldown
FSEL0 FSEL1 FSEL2 QB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷8
÷6
÷8
÷4
÷16
÷8
÷4
D
Q
QFB
FSEL[0:2]
Pulldown
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
20
41
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
GND
QFB
FB
nMAN/A
V
DD
CLK0
CLK1
V
DDA
nALARM0
nALARM1
CLK_IND
GND
V
DD
GND
QB0
QB1
V
DD
GND
QB2
QB3
V
DD
GND
QB4
QB5
V
DD
FSEL3
Pulldown
nALARM0
nALARM1
CLK_IND
879893
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2017 Integrated Device Technology, Inc.
1
Revision B, January 10, 2017
879893 Datasheet
Block Diagram
1
REF
CLK1
Pulldown
1
D
Q
6
QA0:QA5
CLK0
Pulldown
0
PLL
VCO R
ANGE
240MHz - 500MHz
FB
0
FB
Pulldown
REF_SEL
Pulldown
nMAN/A
Pullup
nALARM_RST
Pullup
IDCS
DATA
GENERATOR
D
Q
6
QB0:QB5
nPLL_EN
Pulldown
FSEL[0:3]
Pulldown
D
Q
QFB
nALARM0
nALARM1
CLK_IND
nOE/MR
Pulldown
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Table 1. Pin Descriptions
Number
1, 12, 16,
20, 29, 32,
37, 41, 45
2
3
Name
GND
QFB
FB
Power
Output
Input
Pulldown
Type
Description
Power supply ground.
Clock feedback output. LVCMOS / LVTTL interface levels.
Feedback control input. LVCMOS / LVTTL interface levels.
Manual alarm input. Selects automatic switch mode or manual reference
clock. Clock failure detection, and nALARM_RST and CLK_IND output
flags are enabled. When LOW, IDCS is disabled. When HIGH, IDCS is
enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation
requires nPLL_EN = 0. LVCMOS / LVTTL interface levels.
Core supply pins.
Pulldown
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Analog supply pin.
When LOW, indicates clock failure on CLK0.
LVCMOS / LVTTL interface levels.
When LOW, indicates clock failure on CLK1.
LVCMOS / LVTTL interface levels.
Indicates currently selected input reference clock. When LOW, CLK0 is the
reference clock. When HIGH, CLK1 is the reference clock.
LVCMOS / LVTTL interface levels.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
Active High Master Reset. Active Low Output Enable. When logic LOW,
the internal dividers and the outputs are enabled. When logic HIGH, the
internal dividers are reset and the outputs are in a high-impedance state.
LVCMOS / LVTTL interface levels.
Clock frequency selection and configuration of clock divider modes.
LVCMOS / LVTTL interface levels.
Selects PLL or static test mode. When LOW, PLL is enabled. When HIGH,
PLL is bypassed and IDCS is disabled. The VCO output is replaced by the
reference clock signal fREF. LVCMOS / LVTTL interface levels.
Selects the primary reference clock. When LOW, selects CLK0 as the
primary clock source. When HIGH, selects CLK1 as the primary clock
source. LVCMOS / LVTTL interface levels.
Resets the alarm flags and selected reference clock.
LVCMOS / LVTTL interface levels.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
4
nMAN/A
Input
Pullup
5, 13, 17,
21, 25, 36,
40, 44, 48
6, 7
8
9
10
V
DD
CLK0, CLK1
V
DDA
nALARM0
nALARM1
Power
Input
Power
Output
Output
11
14, 15, 18,
19, 22, 23
CLK_IND
QB5, QB4, QB3,
QB2, QB1, QB0
Output
Output
26
nOE/MR
Input
Pulldown
27, 28,
30, 31
33
FSEL3, FSEL2,
FSEL1, FSEL0
nPLL_EN
Input
Pulldown
Input
Pulldown
34
REF_SEL
Input
Pulldown
35
38, 39 42,
43, 46, 47
nALARM_RST
QA0, QA1, QA2,
QA3, QA4, QA5
Input
Output
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
V
DD
= 3.465V
V
DD
= 2.625V
Test Conditions
Minimum
Typical
4
9
9
51
51
14
Maximum
Units
pF
pF
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
Output Impedance
Function Tables
Table 3. Clock Frequency Function Table
Inputs
FSEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FSEL1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FSEL2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSEL3
0
15 – 25
1
0
30 – 50
1
0
40 – 66.66
1
0
30 – 62.5
1
0
60 – 100
1
0
15 – 31.25
1
0
30 – 62.5
1
0
60 – 100
1
f
REF
60 – 100
f
REF
30 – 62.5
f
REF
15 – 31.25
f
REF
* 2
120 – 200
f
REF
* 2
60 – 125
f
REF
* 3
120 – 200
f
REF
* 4
120 – 200
f
REF
* 8
120 – 200
f
REF
Range
(MHz)
Outputs
Ratio
fQAx (MHz)
Ratio
f
REF
* 8
f
REF
* 4
f
REF
* 4
f
REF
* 2
f
REF
* 3
f
REF
* 3 ÷ 2
f
REF
* 2
f
REF
* 1
f
REF
* 2
f
REF
f
REF
f
REF
÷ 2
f
REF
f
REF
÷ 2
f
REF
f
REF
÷ 2
fQBx (MHz)
120 – 200
60 – 100
120 – 200
60 – 100
120 – 200
60 – 100
60 – 125
30 – 75
120 – 200
60 – 100
15 – 31.25
7.5 – 15.62
20 – 62.5
15 – 31.25
60 – 100
30 – 50
QFB
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
f
REF
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Positive Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
195
13
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Positive Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
173
13
Units
V
V
mA
©2017 Integrated Device Technology, Inc.
5
Revision B, January 10, 2017
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