assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated
Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
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Performance Summary
Read Transaction Timings
Maximum Clock Rate at 1.8V V
CC
/V
CC
Q
Maximum Clock Rate at 3.0V V
CC
/V
CC
Q
Maximum Access Time, (t
ACC
@ 166MHz)
Maximum CS# Access Time to first word @ 166MHz (excluding refresh latency)
166MHz
100MHz
36 ns
56 ns
Maximum Current Consumption
Burst Read or Write (linear burst at 166MHz, 1.8V)
Power On Reset
Standby (CS# = High, 3V, 105°C)
Deep Power Down (CS# = High, 3V, 105°C)
Standby (CS# = High, 1.8V, 105°C)
Deep Power Down (CS# = High, 1.8V, 105°C)
60mA
50mA
300uA
20uA
300uA
10uA
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1.
General Description
The ISSI HyperRAM family of products are high-speed CMOS, Self-refresh Dynamic RAM (DRAM) devices,
with a HyperBus interface.
The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control
logic within the device manages the refresh operations on the RAM array when the memory is not being
actively read or written by the HyperBus interface master (host). Since the host is not required to manage any
refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain
data without refresh. Hence, the memory can also be described as Pseudo Static RAM (PSRAM).
Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that
the host not perform read or write burst transfers that are long enough to block the necessary internal logic
refresh operations when they are needed. The host is required to limit the duration of transactions and allow
additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh
operation is needed.
HyperBus is a low signal count, Double Data Rate (DDR) interface, that achieves high speed read and write
throughput. The DDR protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read
or write transaction on HyperBus consists of a series of 16-bit wide, one clock cycle data transfers at the
internal HyperRAM core with two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ
signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN) device versions are
available for core (V
CC
) and IO buffer (V
CC
Q) supplies of either 1.8V or 3.0V (nominal).
Command, Address, and Data information is transferred over the eight HyperBus DQ signals. The clock is
used for information capture by a HyperBus device when receiving Command-Address/Data on the DQ
signals. Command-Address values are center aligned with clock edges.
The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates:
– when data will start to transfer from the memory to the host in read transactions (initial read latency),
– when data is being transferred from the memory to the host during read data transfers (source
synchronous read data strobe),
– when data will start to transfer from the host to the memory in write transactions (initial write latency),
– and data masking during write data transfers.
During the command and address cycles of a read or write transaction, RWDS acts as an output from the
memory to indicate whether additional initial access latency is needed to perform a dynamic memory refresh
operation.
During read data transfers, RWDS is a read data strobe with data values edge aligned with the transitions of
RWDS driven by the memory device.
During write data transfers, RWDS indicates whether a data byte is masked (prevented from changing the
byte location in memory) or not masked (written to memory). Data masking may be used by the host to byte
align write data within the memory or to enable merging of multiple non-word aligned writes in a single burst
write. During write transactions, data is center aligned with the clock.
Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle.
Each individual read or write transaction can use either a wrapped or linear burst sequence. During wrapped
transactions, accesses start at a selected location and continue to the end of a configured word group aligned
boundary, then wrap to the beginning location in the group, then continue back to the starting location.
Wrapped bursts are generally used for critical word first instruction or data cache line fill read accesses.
During linear transactions, accesses start at a selected location and continue in a sequential manner until the
transaction is terminated when CS# returns High. Linear transactions are generally used for large contiguous
data transfers such as graphic image moves. Since each transaction command selects the type of burst
sequence for that access, wrapped and linear burst transactions can be dynamically intermixed as needed.
For additional information on HyperBus interface operation, please refer to the HyperBus specification.
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2. HyperRAM Product Overview
The HyperRAM
TM
Family consists of multiple density option, 1.8V or 3.0V core and I/O, synchronous self-
refresh Dynamic RAM (DRAM) memory devices. This family provides a HyperBus slave interface to the host
system. HyperBus has an 8 bit (1 byte) wide DDR data bus and uses only word-wide (16-bit data) address
boundaries. Read transactions provide 16 bits of data during each clock cycle (8 bits on both clock edges).
Write transactions take 16 bits of data from each clock cycle (8 bits on each clock edge).
Figure 2.1
HyperRAM Interface
RESET#
CS#
CK
CK#
V
CC
V
CC
Q
DQ[7:0]
RWDS
V
SS
V
SS
Q
Read and write transactions require two clock cycles to define the target row address and burst type, then an
initial access latency of t
ACC
. During the Command-Address (CA) part of a transaction, the memory will
indicate whether an additional latency for a required refresh time (t
RFH
) is added to the initial latency; by
driving the RWDS signal to the High state. During the CA period the third clock cycle will specify the target
word address within the target row. During a read (or write) transaction, after the initial data value has been
output (or input), additional data can be read from (or written to) the row on subsequent clock cycles in either
a wrapped or linear sequence. When configured in linear burst mode, the device will automatically fetch the
next sequential row from the memory array to support a continuous linear burst. Simultaneously accessing
the next row in the array while the read or write data transfer is in progress, allows for a linear sequential burst
operation that can provide a sustained data rate of 333 MB/s (1 byte
(8 bit data bus)
* 2
(data clock edges)
*
166 MHz = 333 MB/s).
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3.
HyperBus
™
Interface
For the general description of how the HyperBus interface operates in HyperRAM memories, refer to the
HyperBus specification. The following section describes HyperRAM device dependent aspects of HyperBus
interface operation.
All bus transactions can be classified as either read or write. A bus transaction is started with CS# going Low
with CK = Low and CK# = High. The transaction to be performed is presented to the HyperRAM device during
the first three clock cycles in a DDR manner using all six clock edges. These first three clocks transfer three
words of Command / Address (CA0, CA1, CA2) information to define the transaction characteristics:
Read or write transaction.
Whether the transaction will be to the memory array or to register space.
Whether a read transaction will use a linear or wrapped burst sequence.
The target half-page address (row and upper order column address).
The target Word (within half-page) address (lower order column address).
Once the transaction has been defined, a number of idle clock cycles are used to satisfy initial read or write
access latency requirements before data is transferred. During the Command-Address portion of all
transactions, RWDS is used by the memory to indicate whether additional initial access latency will be
inserted for a required refresh of the memory array.
When data transfer begins, read data is edge aligned with RWDS transitions or write data is center aligned
with clock transitions. During read data transfer, RWDS serves as a source synchronous data timing strobe.
During write data transfer, clock transitions provide the data timing reference and RWDS is used as a data
mask. When RWDS is Low during a write data transfer, the data byte is written into memory; if RWDS is High
during the transfer the byte is not written.
Data is transferred as 16-bit values with the first eight bits transferred on a High going CK (write data or CA
bits) or RWDS edge (read data) and the second eight bits being transferred on the Low going CK or RWDS
edge. Data transfers during read or write operations can be ended at any time by bringing CS# High when CK
= Low and CK# = High.
The clock may stop in the idle state while CS# is High.
The clock may also stop in the idle state for short periods while CS# is Low, as long as this does not cause a
transaction to exceed the CS# maximum time low (t
CSM
) limit. This is referred to as Active Clock Stop mode.
In some HyperBus devices this mode is used for power reduction. However, due to the relatively short t
CSM
period for completing each data transfer, the Active Clock Stop mode is generally not useful for power
reduction but, may be used for short duration data flow control by the HyperBus master.
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