1. Assumes 8.0 pF load and 1.1 GHz input frequency (typical), I
O
at V
CC
= 5.0 V and T
A
= 25°C.
D
In
In
C
Q
Q
D
C
Q
Q
D
C
Q
Q
1
D
0
C
SW1
SW3
SW2
Q
C
Q
C
Q
C
Q
Out
Q
D
Q
D
Q
D
Q
Figure 1. Logic Diagram
V
CC
= 4.5 to 5.5 V
C3
Sine Wave Generator
C1
In
50
W
V
CC
SW1
SW2
SW3
C2
In
Gnd
Out
C
L
R
L
External Components
C1 = C2 = 1000 pF
C3 = 0.1
mF
C
L
= 8.0 pF (Including Scope and Jig Capacitance)
R
L
= 820
W
for
÷10
at 1.1 GHz
Figure 2. AC Test Circuit
http://onsemi.com
2
MC12080
+15.0
+10.0
+5.0
0
-5.0
AMPLITUDE (dBm)
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-45.0
-50.0
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (MHz)
Divide Ratio = 10; V
CC
= 5.0 V; T
A
= 25°C
+1257.40
+707.11
+397.64
800
400
0
1800
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (MHz)
Figure 4. Output Amplitude versus Input Frequency
ORDERING INFORMATION
Device
MC12080DG
MC12080DR2G
Package
SOIC−8
(Pb−Free)
Shipping
†
98 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
3
mVpp
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
OPERATING
WINDOW
+223.61
+125.74
+70.71
mVrms
+39.76
+22.36
+12.57
+7.07
+3.98
+2.24
+1.26
+0.71
1800
Figure 3. Input Signal Amplitude versus Input Frequency
2000
1600
1200
MC12080
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
A
8
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
_
8
_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
_
8
_
0.010
0.020
0.228
0.244
B
1
S
4
0.25 (0.010)
M
Y
M
−Y−
G
K
C
−Z−
H
D
0.25 (0.010)
M
SEATING
PLANE
N
X 45
_
0.10 (0.004)
M
J
Z Y
S
X
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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