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74AUP1G332GM-G

产品描述Logic Gates 1.8V SINGLE LOW-POW 3-INPUT OR
产品类别逻辑    逻辑   
文件大小196KB,共19页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
标准
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74AUP1G332GM-G概述

Logic Gates 1.8V SINGLE LOW-POW 3-INPUT OR

74AUP1G332GM-G规格参数

参数名称属性值
Source Url Status Check Date2013-06-14 00:00:00
是否无铅含铅
是否Rohs认证符合
厂商名称NXP(恩智浦)
Reach Compliance Codeunknown
Base Number Matches1

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74AUP1G332
Low-power 3-input OR-gate
Rev. 5 — 4 July 2012
Product data sheet
1. General description
The 74AUP1G332 provides a single 3-input OR gate.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C

74AUP1G332GM-G相似产品对比

74AUP1G332GM-G 74AUP1G332GW-G
描述 Logic Gates 1.8V SINGLE LOW-POW 3-INPUT OR Logic Gates 1.8V SINGLE LOW-POW 3-INPUT OR
Source Url Status Check Date 2013-06-14 00:00:00 2013-06-14 00:00:00
是否Rohs认证 符合 符合
厂商名称 NXP(恩智浦) NXP(恩智浦)
Reach Compliance Code unknown unknown
Base Number Matches 1 1

 
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