SE98
DDR memory module temp sensor, 3.3 V
Rev. 04 — 2 February 2009
Product data sheet
1. General description
The NXP Semiconductors SE98 measures temperature from
−40 °C
to +125
°C
communicating via the I
2
C-bus/SMBus. It is typically mounted on a Dual In-line Memory
Module (DIMM) measuring the DRAM temperature in accordance with the new JEDEC
(JC-42.4)
Mobile Platform Memory Module Thermal Sensor Component
specification.
Placing the Temp Sensor (TS) on DIMM allows accurate monitoring of the DIMM module
temperature to better estimate the DRAM case temperature (T
case
) to prevent it from
exceeding the maximum operating temperature of 85
°C.
The chip set throttles the
memory traffic based on the actual temperatures instead of the calculated worst-case
temperature or the ambient temperature using a temp sensor mounted on the
motherboard. There is up to a 30 % improvement in thin and light notebooks that are
using one or two 1G SO-DIMM modules, although other memory modules such as in
server applications will also see an increase in system performance. Future uses of the
TS will include more dynamic control over thermal throttling, the ability to use the Alarm
Window to create multiple temperature zones for dynamic throttling and to save processor
time by scaling the memory refresh rate.
The TS consists of an Analog-to-Digital Converter (ADC) that monitors and updates its
own temperature readings 8 times per second, converts the reading to a digital data, and
latches them into the data temperature registers. User-programmable registers, such as
Shutdown or Low-power modes and the specification of temperature event and critical
output boundaries, provide flexibility for DIMM temperature-sensing applications.
When the temperature changes beyond the specified boundary limits, the SE98 outputs
an EVENT signal. The user has the option of setting the EVENT output signal polarity as
either an active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can even be configured as a critical temperature output.
The SE98 supports the industry-standard 2-wire I
2
C-bus/SMBus serial interface. The
SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and
Device ID registers provide the ability to confirm the identify of the device. Three address
pins allow up to eight devices to be controlled on a single bus. To maintain
interchangeability with the I
2
C-bus/SMBus interface the electrical specifications are
specified with the operating voltage of 3.0 V to 3.6 V.
NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
2. Features
2.1 General features
I
I
I
I
I
I
JEDEC (JC-42.4) SO-DIMM temperature sensor
Optimized for voltage range: 3.0 V to 3.6 V
Shutdown/Standby current: 8
µA
(typ.) and 15
µA
(max.)
2-wire interface: I
2
C-bus/SMBus compatible, 0 Hz to 400 kHz
SMBus ALERT and TIMEOUT (programmable)
Available packages: TSSOP8 and HVSON8
2.2 Temperature sensor features
I
I
I
I
I
Temperature-to-Digital converter
Operating current: 200
µA
(typ.) and 250
µA
(max.)
Programmable hysteresis threshold: 0
°C,
1.5
°C,
3
°C,
6
°C
Over/under/critical temperature EVENT output
C grade accuracy:
N
±1 °C/±2 °C
(typ./max.)
→
+75
°C
to +95
°C
N
±2 °C/±3 °C
(typ./max.)
→
+40
°C
to +125
°C
N
±3 °C/±4 °C
(typ./max.)
→ −40 °C
to +125
°C
3. Applications
I
I
I
I
DDR2 and DDR3 memory modules
Laptops, personal computers and servers
Enterprise networking
Hard disk drives and other PC peripherals
4. Ordering information
Table 1.
Ordering information
Topside
mark
SE98
SE98
Package
Name
TSSOP8
HVSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 4.4 mm
plastic thermal enhanced very thin small outline package;
no leads; 8 terminals; body 3
×
3
×
0.85 mm
Version
SOT530-1
SOT908-1
Type number
SE98PW
SE98TK
SE98_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2009
2 of 39
NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
5. Block diagram
SE98
REGISTERS
A0
CRITICAL TEMPERATURE LIMIT
LOCK
PROTECT
UPPER TEMPERATURE LIMIT
LOWER TEMPERATURE LIMIT
HYSTERESIS THRESHOLD
TEMPERATURE
REGISTER
11-BIT
∆Σ
ADC
BAND GAP
TEMPERATURE
SENSOR
V
DD
A1
A2
MANUFACTURER ID
DEVICE ID
DEVICE CAPABILITY REGISTER
CONTROL LOGIC
EVENT
CONFIGURATION REGISTER
V
SS
EVENT OUTPUT COMPARATOR/INT MODE
EVENT OUTPUT POLARITY
ENABLE/DISABLE EVENT OUTPUT
EVENT OUTPUT STATUS
SENSOR ENABLE/SHUTDOWN
I
2
C-bus/SMBus
INTERFACE
SCL
SDA
POR
CIRCUIT
002aab280
Fig 1.
Block diagram of SE98
SE98_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2009
3 of 39
NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
6. Pinning information
6.1 Pinning
terminal 1
index area
A0
A1
A2
A0
A1
A2
V
SS
1
2
3
4
002aab806
1
2
8
7
V
DD
EVENT
SCL
SDA
SE98TK
3
4
6
5
8
V
DD
EVENT
SCL
SDA
002aab804
SE98PW
7
6
5
V
SS
Transparent top view
Fig 2.
Pin configuration for TSSOP8
Fig 3.
Pin configuration for HVSON8
6.2 Pin description
Table 2.
Symbol
A0
[1]
A1
A2
V
SS
SDA
SCL
EVENT
V
DD
[1]
Pin description
Pin
1
2
3
4
5
6
7
8
Type
I
I
I
ground
I/O
I
O
power
Description
I
2
C-bus/SMBus slave address bit 0
I
2
C-bus/SMBus slave address bit 1
I
2
C-bus/SMBus slave address bit 2
device ground
SMBus/I
2
C-bus serial data input/output (open-drain).
Must have external pull-up resistor.
SMBus/I
2
C-bus serial clock input/output (open-drain).
Must have external pull-up resistor.
Thermal alarm output for high/low and critical temperature
limit (open-drain). Must have external pull-up resistor.
device power supply (3.0 V to 3.6 V)
In general, application of 10 V on the A0 pin would not damage the pin, but NXP Semiconductors does not
guarantee the overvoltage for this pin.
SE98_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2009
4 of 39
NXP Semiconductors
SE98
DDR memory module temp sensor, 3.3 V
7. Functional description
7.1 Serial bus interface
The SE98 uses the 2-wire serial bus (I
2
C-bus/SMBus) to communicate with a host
controller. The serial bus consists of a clock (SCL) and data (SDA) signals. The device
can operate on either the I
2
C-bus Standard/Fast mode or SMBus. The I
2
C-bus
Standard-mode is defined to have bus speeds from 0 Hz to 100 kHz, I
2
C-bus Fast-mode
from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master
generates the SCL signal, and the SE98 uses the SCL signal to receive or send data on
the SDA line. Data transfer is serial, bidirectional, and is one bit at a time with the Most
Significant Bit (MSB) transferred first, and a complete I
2
C-bus data is 1 byte. Since SCL
and SDA are open-drain, pull-up resistors must be installed on these pins.
7.2 Slave address
The SE98 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address
that allows a total of eight devices to co-exist on the same bus. The input of each pin is
sampled at the start of each I
2
C-bus/SMBus access. The temperature sensor’s fixed
address is 0011.
slave address
MSB
0
0
1
1
A2
A1
LSB
A0
R/W
X
fixed
hardware
selectable
002aab304
Fig 4.
Slave address
SE98_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2009
5 of 39
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