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8T49N285-998NLGI8

产品描述Clock Synthesizer / Jitter Cleaner Universal Frequency Translator
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小1MB,共67页
制造商IDT (Integrated Device Technology)
标准
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8T49N285-998NLGI8概述

Clock Synthesizer / Jitter Cleaner Universal Frequency Translator

8T49N285-998NLGI8规格参数

参数名称属性值
Brand NameIntegrated Device Technology
是否无铅不含铅
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
零件包装代码VFQFPN
包装说明VFQFN-56
针数56
制造商包装代码NLG56P2
Reach Compliance Codecompliant
其他特性IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY
JESD-30 代码S-XQCC-N56
JESD-609代码e3
长度8 mm
湿度敏感等级3
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
最大输出时钟频率1000 MHz
封装主体材料UNSPECIFIED
封装代码HVQCCN
封装形状SQUARE
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)260
主时钟/晶体标称频率40 MHz
座面最大高度1 mm
最大供电电压2.625 V
最小供电电压2.375 V
标称供电电压2.5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度8 mm
uPs/uCs/外围集成电路类型CLOCK GENERATOR, PROCESSOR SPECIFIC

文档解析

8T49N285是一款集成设备技术公司(Integrated Device Technology, Inc.)生产的多功能相位锁定环(PLL)芯片,它在不同频率下的性能表现可以通过其数据手册中的AC(交流)特性表来了解。以下是一些关键的性能指标和测试数据摘要:

  1. 输出频率(fOUT):该芯片支持的输出频率范围从8kHz到1GHz不等,具体取决于输出分频器的设置。

  2. 输出上升和下降时间(tR / tF):在不同输出类型(如LVPECL、LVDS、HCSL、LVCMOS)下,上升和下降时间会有所不同。例如,对于LVPECL输出,20%到80%的上升和下降时间在145ps到600ps之间。

  3. 输出斜率(SR):斜率是衡量输出信号变化速率的一个指标,对于LVPECL输出,斜率在1V/ns到5V/ns之间。

  4. 输出占空比(odc):占空比是指输出信号高电平时间与整个周期时间的比例。对于LVPECL、LVDS、HCSL输出,占空比在45%到55%之间。

  5. 初始频率偏移:在切换或进入/离开保持状态时,初始频率偏移在-50ppb到50ppb之间。

  6. 相位抖动(tjit(φ)):RMS(均方根)相位抖动是衡量输出信号稳定性的一个重要指标。例如,在122.88MHz输出频率下,LVPECL类型的抖动在279fs到286fs之间。

  7. 杂散限制:在特定频率偏移下,杂散限制(Spurious Limit)是衡量输出信号中不希望的频率分量的一个指标。例如,在>30MHz的偏移下,122.88MHz输出的杂散限制为-83dBc。

  8. 启动时间(tstartup):从VCC超过80%到第一个输出时钟边缘的启动时间,根据是否使用内部OTP(一次性可编程存储器)或外部EEPROM(电子可擦写只读存储器),以及I2C频率的不同,启动时间有所不同。

  9. 静态相位偏移变化(ΔSPO):在特定输入和输出频率下,静态相位偏移的变化范围。

  10. 相位噪声:在不同偏移频率下,相位噪声的典型值。

这些数据通常在数据手册的AC特性表中给出,并且可能会根据不同的输出类型和配置有所变化。具体的测试数据和性能表现,建议参考8T49N285的完整数据手册,其中包含了详细的测试条件和测试结果。如果需要更详细的数据或有特定的测试要求,可以联系芯片的制造商获取更多信息。

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FemtoClock
®
NG Octal Universal
Frequency Translator
8T49N285
Datasheet
Description
The 8T49N285 has a fractional-feedback PLL that can be used as a
jitter attenuator or frequency translator. It is equipped with six integer
and two fractional output dividers, allowing the generation of up to 8
different output frequencies, ranging from 8kHz to 1GHz. Three of
these frequencies are completely independent of each other and the
inputs. The other five are related frequencies. The eight outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G, and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N285 accepts up to two differential or single-ended input
clocks and a crystal input. The PLL can lock to either input clock, but
both input clocks must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS). It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N285 supports holdover with an initial accuracy of ±50ppB
from the point where the loss of all applicable input reference(s) has
been detected. It maintains a historical average operating point that
may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
The PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I
2
C interface. It also supports
I
2
C master capability to allow the register configuration to be read
from an external EEPROM.
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS typical jitter (including spurs),12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover & Loss-of-Signal status outputs
Open-drain Interrupt pin
Nine programmable PLL loop bandwidth settings from 1.4Hz to
360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I
2
C or via external I
2
C EEPROM
Bypass clock paths for system tests
Power supply modes
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free RoHs (6)
Typical Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
©2018 Integrated Device Technology, Inc.
1
January 31, 2018

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是否Rohs认证 符合 符合 - 符合 符合 -
包装说明 VFQFN-56 HVQCCN, - HVQCCN, HVQCCN, -
Reach Compliance Code compliant compliant - compliant compliant -
其他特性 IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY - IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY -
JESD-30 代码 S-XQCC-N56 S-XQCC-N56 - S-XQCC-N56 S-XQCC-N56 -
JESD-609代码 e3 e3 - e3 e3 -
长度 8 mm 8 mm - 8 mm 8 mm -
端子数量 56 56 - 56 56 -
最高工作温度 85 °C 85 °C - 85 °C 85 °C -
最低工作温度 -40 °C -40 °C - -40 °C -40 °C -
最大输出时钟频率 1000 MHz 1000 MHz - 1000 MHz 1000 MHz -
封装主体材料 UNSPECIFIED UNSPECIFIED - UNSPECIFIED UNSPECIFIED -
封装代码 HVQCCN HVQCCN - HVQCCN HVQCCN -
封装形状 SQUARE SQUARE - SQUARE SQUARE -
封装形式 CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE -
峰值回流温度(摄氏度) 260 260 - 260 260 -
主时钟/晶体标称频率 40 MHz 40 MHz - 40 MHz 40 MHz -
座面最大高度 1 mm 1 mm - 1 mm 1 mm -
最大供电电压 2.625 V 2.625 V - 2.625 V 2.625 V -
最小供电电压 2.375 V 2.375 V - 2.375 V 2.375 V -
标称供电电压 2.5 V 2.5 V - 2.5 V 2.5 V -
表面贴装 YES YES - YES YES -
技术 CMOS CMOS - CMOS CMOS -
温度等级 INDUSTRIAL INDUSTRIAL - INDUSTRIAL INDUSTRIAL -
端子面层 Matte Tin (Sn) Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn) -
端子形式 NO LEAD NO LEAD - NO LEAD NO LEAD -
端子节距 0.5 mm 0.5 mm - 0.5 mm 0.5 mm -
端子位置 QUAD QUAD - QUAD QUAD -
处于峰值回流温度下的最长时间 30 30 - 30 30 -
宽度 8 mm 8 mm - 8 mm 8 mm -
uPs/uCs/外围集成电路类型 CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC - CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC -

 
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