SM5951A
8-channel DSD Editing System Signal Processor LSI
OVERVIEW
The SM5951A is an 8-channel DSD (Direct Stream Digital) editing system signal processor LSI. It takes 4
DSD input signals per channel, mixes them, and then converts the result back into 1-bit DSD data for output.
FEATURES
I
I
I
I
I
I
I
I
I
I
DSD signal sampling rate: 5.6448MHz (128
×
44.1kHz) and 2.8224MHz (64
×
44.1kHz) supported
8-channel DSD signal mixing
• 8-channel, 4 DSD signal inputs per channel mixing using arbitrary coefficients for each input
Raw signal switching function (auto bypass)
• Automatically switches to raw signal output with no switching noise and no signal degradation when mix-
ing is not required, bypassing the mixing processing
Input/output format
• Normal input/output format where the data changes are synchronized to the bit clock cycle, and Manches-
ter-type encoding input/output format where the data inverts during the bit clock cycle
Monitor output: Simultaneous 64
×
44.1kHz monitor data output when in 128
×
44.1kHz sampling rate mode
Microcontroller interface: Parallel bi-directional 8-bit/16-bit/32-bit data bus supported
Master clock: 45.1584MHz (1024
×
44.1kHz) or 56.448MHz (1280
×
44.1kHz)
2 voltage supplies: 3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V)
Operating temperature range:
−
20 to 70°C
Package: 160-pin QFP
PACKAGE DIMENSIONS
(Unit: mm)
31.2 ± 0.4
28.0 ± 0.1
0.11 to 0.23
28.0 ± 0.1
0.22 to 0.4
3.35 ± 0.1
0.65
31.2 ± 0.4
0 to 10.0
15
1.6
4.0MAX
0.35
15
0.15
0.8
0.8 ± 0.2
ORDERING INFORMATION
Device
SM5951AF
Package
160-pin QFP
SEIKO NPC CORPORATION —1
SM5951A
PIN DESCRIPTION
Number of
Pins
1
1
1
1
1
1
Name
RST_X
FS
CLK
SEL1280
SELDSDI
SELDSDO
I/O
I
I
I
I
I
I
Polarity
1
PU, S
−
−
PD, S
PD, S
PD, S
Voltage
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
System Reset
1fs Clock (44.1kHz)
Master Clock
Select Master Clock Rate
[HIGH]: 1280
×
44.1kHz, [LOW]: 1024
×
44.1kHz
Select DSD Input Format
[HIGH]: Manchester Encoding, [LOW]: Normal
Select DSD Output Format
[HIGH]: Manchester Encoding, [LOW]: Normal
Select MCU Data Bus Width
[SELBUS1, SELBUS0]
[LOW, LOW]: 8-bit
[LOW, HIGH]: 16-bit
[HIGH,
×
(LOW or HIGH)]: 32-bit
MCU I/F: Chip Select
MCU I/F: Write Enable
MCU I/F: Read Enable
MCU I/F: Address Bus
MCU I/F: Data Bus
DSD Input: Bit Clock IN
DSD Input: DSD CH1 Data (LINE0 to LINE3)
DSD Input: DSD CH2 Data (LINE0 to LINE3)
DSD Input: DSD CH3 Data (LINE0 to LINE3)
DSD Input: DSD CH4 Data (LINE0 to LINE3)
DSD Input: DSD CH5 Data (LINE0 to LINE3)
DSD Input: DSD CH6 Data (LINE0 to LINE3)
DSD Input: DSD CH7 Data (LINE0 to LINE3)
DSD Input: DSD CH8 Data (LINE0 to LINE3)
DSD Input: External Mute Pattern
DSD Output: Bit Clock Out
DSD Output: DSD Output DATA (CH1 to CH8)
DSD 64fs Output: Bit Clock Out
DSD 64fs Output: DSD Output DATA (CH1 to CH8)
SYNC Monitor
IOTEST_EN, SCAN_EN, ATPG_EN, FUNC_MODE etc.
Power Supply (I/O)
Power Supply (Core)
Ground Level
Functional Description
2
SELBUS [1:0]
I
PU, S
3.3V
1
1
1
8
32
1
4
4
4
4
4
4
4
4
1
1
8
1
8
1
8
10
14
24
CS_X
WR_X
RD_X
ADDR [7:0]
DATA [31:0]
BCKI
DSDI1_[3:0]
DSDI2_[3:0]
DSDI3_[3:0]
DSDI4_[3:0]
DSDI5_[3:0]
DSDI6_[3:0]
DSDI7_[3:0]
DSDI8_[3:0]
EXMUTE
BCKO
DSDO [8:1]
BCK64O
DSD64O [8:1]
MOSYNC
TEST [8:1]
VDDH
VDDL
VSS
I
I
I
I
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
−
−
−
PU
PU, S
PU, S
PU
3mA
S
−
−
−
−
−
−
−
−
−
6mA
3mA
6mA
3mA
3mA
PD
−
−
−
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
2.5V
0V
1. Attributes: S
=
Schmitt type, PU
=
with pull-up resistor, PD
=
with pull-down resistor, mA
=
output current
SEIKO NPC CORPORATION —5
单片机
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