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IDT6116LA25TPGI

产品描述Standard SRAM, 2KX8, 25ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
产品类别存储   
文件大小137KB,共12页
制造商IDT (Integrated Device Technology)
标准  
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IDT6116LA25TPGI概述

Standard SRAM, 2KX8, 25ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24

IDT6116LA25TPGI规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
零件包装代码DIP
包装说明DIP, DIP24,.3
针数24
Reach Compliance Codecompliant
ECCN代码EAR99
Is SamacsysN
最长访问时间25 ns
I/O 类型COMMON
JESD-30 代码R-PDIP-T24
JESD-609代码e3
长度31.75 mm
内存密度16384 bit
内存集成电路类型STANDARD SRAM
内存宽度8
功能数量1
端子数量24
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织2KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装等效代码DIP24,.3
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)260
电源5 V
认证状态Not Qualified
座面最大高度4.191 mm
最小待机电流2 V
最大压摆率0.075 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级INDUSTRIAL
端子面层MATTE TIN
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度7.62 mm
Base Number Matches1

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CMOS Static RAM
16K (2K x 8-Bit)
Features
High-speed access and chip select times
– Military: 20/25/35/45/55/70/90/120/150ns (max.)
– Industrial: 20/25/35/45ns (max.)
– Commercial: 15/20/25/35/45ns (max.)
Low-power consumption
Battery backup operation
– 2V data retention voltage (LA version only)
Produced with advanced CMOS high-performance
technology
CMOS process virtually eliminates alpha particle soft-error
rates
Input and output directly TTL-compatible
Static operation: no clocks or refresh required
Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip,
24-pin SOIC and 24-pin SOJ
Military product compliant to MIL-STD-833, Class B
IDT6116SA
IDT6116LA
Description
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-performance,
high-reliability CMOS technology.
Access times as fast as 15ns are available. The circuit also offers a
reduced power standby mode. When
CS
goes HIGH, the circuit will
automatically go to, and remain in, a standby power mode, as long
as
CS
remains HIGH. This capability provides significant system level
power and cooling savings. The low-power (LA) version also offers a
battery backup data retention capability where the circuit typically
consumes only 1µW to 4µW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or
ceramic DIP, 24-lead gull-wing SOIC, and 24-lead J-bend SOJ providing
high board-level packing densities.
Military grade product is manufactured in compliance to the latest
version of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
Functional Block Diagram
A
0
V
CC
ADDRESS
DECODER
A
10
128 X 128
MEMORY
ARRAY
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
,
CS
OE
WE
CONTROL
CIRCUIT
3089 drw 01
NOVEMBER 2006
1
©2006 Integrated Device Technology, Inc.
DSC-3089/06

 
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