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70125S35JG8

产品描述Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
产品类别存储    存储   
文件大小200KB,共16页
制造商IDT (Integrated Device Technology)
标准
下载文档 详细参数 选型对比 全文预览

70125S35JG8概述

Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

70125S35JG8规格参数

参数名称属性值
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
包装说明QCCJ, LDCC52,.8SQ
Reach Compliance Codecompliant
最长访问时间35 ns
I/O 类型COMMON
JESD-30 代码S-PQCC-J52
JESD-609代码e3
内存密度18432 bit
内存集成电路类型DUAL-PORT SRAM
内存宽度9
湿度敏感等级1
功能数量1
端口数量2
端子数量52
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织2KX9
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC52,.8SQ
封装形状SQUARE
封装形式CHIP CARRIER
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
认证状态Not Qualified
最大待机电流0.015 A
最小待机电流2 V
最大压摆率0.25 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Matte Tin (Sn) - annealed
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
Base Number Matches1

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HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
Features
IDT70121S/L
IDT70125S/L
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 35ns (max.)
Low-power operation
– IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY
output flag on Master;
BUSY
input on Slave
INT
flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
10L
A
0L
(1,2)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
Address
Decoder
11
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2654 drw 01
(2)
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-stated push-pull output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is non-tri-stated push-pull output.
AUGUST 2014
1
©2014 Integrated Device Technology, Inc.
DSC 2654/13

70125S35JG8相似产品对比

70125S35JG8 70125S35JGI8 70125S35JGI 70125S35JG 70125L55JGI8 70125L55JGI 70121S55JG 70121S55JG8 70121S55JGI 70121S55JGI8
描述 Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 Dual-Port SRAM Dual-Port SRAM Dual-Port SRAM, 2KX9, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 Dual-Port SRAM, 2KX9, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52 Dual-Port SRAM Dual-Port SRAM
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant compliant compliant
内存集成电路类型 DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM
Base Number Matches 1 1 1 1 1 1 1 1 1 1
是否Rohs认证 符合 符合 符合 符合 - - 符合 符合 - -
包装说明 QCCJ, LDCC52,.8SQ QCCJ, LDCC52,.8SQ QCCJ, LDCC52,.8SQ QCCJ, LDCC52,.8SQ - - QCCJ, LDCC52,.8SQ QCCJ, LDCC52,.8SQ - -
最长访问时间 35 ns 35 ns 35 ns 35 ns - - 55 ns 55 ns - -
I/O 类型 COMMON COMMON COMMON COMMON - - COMMON COMMON - -
JESD-30 代码 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 S-PQCC-J52 - - S-PQCC-J52 S-PQCC-J52 - -
JESD-609代码 e3 e3 e3 e3 - - e3 e3 - -
内存密度 18432 bit 18432 bit 18432 bit 18432 bit - - 18432 bit 18432 bit - -
内存宽度 9 9 9 9 - - 9 9 - -
湿度敏感等级 1 1 1 1 - - 1 1 - -
功能数量 1 1 1 1 - - 1 1 - -
端口数量 2 2 2 2 - - 2 2 - -
端子数量 52 52 52 52 - - 52 52 - -
字数 2048 words 2048 words 2048 words 2048 words - - 2048 words 2048 words - -
字数代码 2000 2000 2000 2000 - - 2000 2000 - -
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS - - ASYNCHRONOUS ASYNCHRONOUS - -
最高工作温度 70 °C 85 °C 85 °C 70 °C - - 70 °C 70 °C - -
组织 2KX9 2KX9 2KX9 2KX9 - - 2KX9 2KX9 - -
输出特性 3-STATE 3-STATE 3-STATE 3-STATE - - 3-STATE 3-STATE - -
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - - PLASTIC/EPOXY PLASTIC/EPOXY - -
封装代码 QCCJ QCCJ QCCJ QCCJ - - QCCJ QCCJ - -
封装等效代码 LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ LDCC52,.8SQ - - LDCC52,.8SQ LDCC52,.8SQ - -
封装形状 SQUARE SQUARE SQUARE SQUARE - - SQUARE SQUARE - -
封装形式 CHIP CARRIER CHIP CARRIER CHIP CARRIER CHIP CARRIER - - CHIP CARRIER CHIP CARRIER - -
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL - - PARALLEL PARALLEL - -
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED - -
电源 5 V 5 V 5 V 5 V - - 5 V 5 V - -
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified - - Not Qualified Not Qualified - -
最大待机电流 0.015 A 0.005 A 0.005 A 0.015 A - - 0.015 A 0.015 A - -
最小待机电流 2 V 2 V 2 V 2 V - - 2 V 2 V - -
最大压摆率 0.25 mA 0.21 mA 0.21 mA 0.25 mA - - 0.24 mA 0.24 mA - -
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V - - 5.5 V 5.5 V - -
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V - - 4.5 V 4.5 V - -
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V - - 5 V 5 V - -
表面贴装 YES YES YES YES - - YES YES - -
技术 CMOS CMOS CMOS CMOS - - CMOS CMOS - -
温度等级 COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL - - COMMERCIAL COMMERCIAL - -
端子面层 Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed - - Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed - -
端子形式 J BEND J BEND J BEND J BEND - - J BEND J BEND - -
端子节距 1.27 mm 1.27 mm 1.27 mm 1.27 mm - - 1.27 mm 1.27 mm - -
端子位置 QUAD QUAD QUAD QUAD - - QUAD QUAD - -
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED - -

 
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