Parallel Bidirectional FIFO
512 x 18 and 1,024 x 18
IDT72511
IDT72521
NOTE: The IDT72511/72521 have been obsoleted and the last time buy will be
on 01/29/2003. These devices should not be used in new designs.
FEATURES:
•
DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated first-in, first-out memo-
ries that enhance processor-to-processor and processor-to-peripheral com-
munications. IDT BiFIFOs integrate two side-by-side memory arrays for data
transfers in two directions.
The BiFIFOs have two ports, A and B, that both have standard micropro-
cessor interfaces. All BiFIFO operations are controlled from the 18-bit wide
Port A. Port B is also 18 bits wide and can be connected to another processor
or a peripheral controller. The BiFIFOs have a 9-bit bypass path that allows
the device connected to Port A to pass messages directly to the Port B device.
Ten registers are accessible through Port A, Command Register, a Status
Register, and eight Configuration Registers.
The IDT BiFIFO has programmable flags. Each FIFO memory array has
four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of
eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to
any depth through the Configuration Registers. These eight internal flags can
be assigned to any of four external flag pins (FLG
A
-FLG
D
) through one
Configuration Register.
Port B has programmable I/O, reread/rewrite and DMA functions. Six
programmable I/O pins are manipulated through two Configuration Registers.
The Reread and Rewrite controls will read or write Port B data blocks multiple
times. The BiFIFO has three pins, REQ, ACK and CLK, to control DMA
transfers from Port B devices.
Two side-by-side FIFO memory arrays for bidirectional data
transfers
•
512 x 18-Bit - 512 x 18-Bit (IDT72511)
•
1,024 x 18-Bit - 1,024 x 18-Bit (IDT72521)
•
18-bit data buses on Port A side and Port B side
•
Can be configured for 18-to-18-bit or 36-to-36-bit
communication
•
Fast 35ns access time
•
Fully programmable standard microprocessor interface
•
Built-in bypass path for direct data transfer between two ports
•
Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
•
Two programmable flags, Almost-Empty and Almost-Full for
each FIFO
•
Programmable flag offset can be set to any depth in the FIFO
•
Any of the eight flags can be assigned to four external flag pins
•
Flexible reread/rewrite capabilities
•
Six general-purpose programmable I/O pins
•
Standard DMA control pins for data exchange with peripherals
•
68-pin PLCC package
•
Industrial temperature range (–40
ο
C to +85
ο
C) is available
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
18-bits
Data
18-bits
Data
Bypass
9-bits
Port
A
18-Bit
FIFO
Port
B
Programmable
I/O Logic
I/O
Control
Processor
Interface
A
Programmable
Flag Logic
Registers
Processor
Interface
B
Handshake
Interface
Control
Flags
DMA
2668 drw 01
FEBRUARY 2002
1
©
2002 Integrated Device Technology, Inc.
DSC-2668/8
IDT72511/72521 Parallel BiFIFO
512 x18, 1,024 x 18
Commercial Temperature Range
PIN CONFIGURATIONS
D
A4
D
A3
D
A2
D
A1
D
A0
PIO
1
PIO
0
CS
A
R/W
A
GND
RER
REW
REQ
ACK
CLK
D
B0
D
B1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
INDEX
D
A5
D
A6
D
A7
D
A16
PIO
2
LDREW
GND
RS
V
CC
DS
A
GND
LDRER
PIO
3
D
A8
D
A9
D
A10
PIO
4
D
B2
D
B3
D
B4
D
B5
D
B6
D
B7
D
B16
W
B
(R/W
B
)
V
CC
R
B
(DS
B
)
GND
GND
D
B8
D
B9
D
B10
D
B11
D
B12
PIO
5
D
A11
D
A12
D
A13
D
A14
D
A15
D
A17
A
0
A
1
FLG
D
FLG
C
FLG
B
FLG
A
D
B17
D
B15
D
B14
D
B13
PLCC (J68-1, order code: J)
TOP VIEW
2
2668 drw 02
IDT72511/72521 Parallel BiFIFO
512 x18, 1,024 x 18
Commercial Temperature Range
PIN DESCRIPTION
Symbol
D
A0-
D
A17
CS
A
DS
A
R/W
A
A
0
, A
1
D
B0
-D
B17
R
B
(DS
B)
Name
Data A
Chip Select A
Data Strobe A
Read/Write A
Addresses
Data B
Read B
I/O
I/O
I
I
I
I
I/O
Data inputs and outputs for the 18-bit Port A bus.
Port A is accessed when Chip Select A is LOW.
Description
Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge
of Data Strobe when Chip Select is LOW.
This pin controls the read or write direction of Port A. When
CS
A
is LOW and R/W
A
is HIGH, data is read from Port A on the falling
edge of
DS
A
. When
CS
A
is LOW and R/W
A
is LOW, data is written into Port A on the rising edge of
DS
A
.
When Chip Select A is asserted, A
0
, A
1
, and Read/Write A are used to select one of six internal resources.
Data inputs and outputs for the 18-bit Port B bus.
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin
functions as an output. This pin can function as part of an Intel-style interface (R
B
) or as part of a Motorola-style interface (DS
B
). As an
Intel-style interface, data is read from Port B on a falling edge of
R
B.
As a Motorola-style interface, data is read on the falling edge of
DS
B
or written on the rising edge of
DS
B
through Port B. The default is Intel-style processor mode. (R
B
as an input).
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin
functions as an output. This pin can function as part of an Intel-style interface (W
B
) or as part of a Motorola-style interface (R/W
B
). As
an Intel-style interface, data is written to Port B on a rising edge of
W
B
. As a Motorola-style interface, data is read (R/W
B
= HIGH)
or written (R/W
B
= LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The default is Intel-style processor
mode (W
B
as an input.)
I
I
I
I
I
O
I
O
Loads A→B FIFO Read Pointer with the value of the Reread Pointer when LOW.
Loads B→A FIFO Write Pointer with the value of the Rewrite Pointer when LOW.
Loads the Reread Pointer with the value of the A→B FIFO Read Pointer when HIGH.
Loads the Rewrite Pointer with the value of the B→A FIFO Write Pointer when HIGH.
When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active
HIGH or active LOW.
When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This confirms that a data
transfer may begin. Acknowledge can be programmed either active HIGH or active LOW.
This pin is used to generate timing for ACK,
R
B
,
W
B
,
DS
B
and R/W
B
when Port B is in the peripheral mode.
These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each of the two internal FIFOs (A→B and
B→A) has four internal flags: Empty, Almost-Empty, Almost-Full and Full.
Six general purpose I/O pins. The input or output direction of each pin can be set independently.
A LOW on this pin will perform a reset of all BiFIFO functions.
There are two +5V power pins.
There are five Ground pins at 0V.
W
B
(R/W
B)
Write B
RER
REW
LDRER
LDREW
REQ
ACK
CLK
Reread
Rewrite
Load Reread
Load Rewrite
Request
Acknowledge
Clock
FLG
A
-FLG
D
Flags
PIO
0
-PIO
5
Programmable I/O
Inputs/ Outputs
RS
V
CC
GND
Reset
Power
Ground
I
3
IDT72511/72521 Parallel BiFIFO
512 x18, 1,024 x 18
Commercial Temperature Range
DETAILED BLOCK DIAGRAM
Reread Pointer
CS
A
DS
A
R/W
A
A
1
A
0
Load Reread
Port A
Control
Write Pointer
Reread
Read Pointer
Port B
Control
LDRER
LDREW
RER
REW
R
B
(DS
B
) ==
W
B
(R/W
B
) ==
A
18
B FIFO
18
Bypass Path
Port A
D
A0
-D
A17
9
9
Port B
D
B0
-D
B17
B
18
A FIFO
18
Read Pointer
Load Rewrite
Write Pointer
Rewrite
Rewrite Pointer
16
FLGA*
FLGB*
FLGC*
FLGD*
Command
Status
Configuration 0
Reset
RS
REQ*
ACK*
CLK
Programmable
Flag Logic
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
DMA
Control
Programmable
I/O Logic
PIO5 ==
PIO4 ==
PIO3 ==
PIO2 ==
PIO1 ==
PIO0 ==
2668 drw 03
NOTES:
(*) Can be programmed either active high or active low in internal configuration registerers.
(==) Can be programmed through an internal configuration register to be either an input or an output.
4
IDT72511/72521 Parallel BiFIFO
512 x18, 1,024 x 18
Commercial Temperature Range
FUNCTIONAL DESCRIPTION
IDT’s BiFIFO family is versatile for both multiprocessor and peripheral
applications. Data can be sent through both FIFO memories concurrently,
thus freeing both processors from laborious direct memory access (DMA)
protocols and frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the IDT BiFIFO, making
simultaneous data exchange possible. Each FIFO is monitored by separate
internal read and write pointers, so communication is not only bidirectional, it
is also totally independent in each direction. The processor connected to Port
A of the BiFIFO can send or receive messages directly to the Port B device
using the BiFIFO’s 9-bit bypass path.
The BiFIFO can be used in different bus configurations: 18 bits to 18
bits and 36 bits to 36 bits. One BiFIFO can be used for the 18- to 18-bit
configuration, and two BiFIFOs are required for 36- to 36-bit configuration.
This configuration can be extended to wider bus widths (54- to 54-bits, 72-
to 72-bits, …) by adding more BiFIFOs to the configuration.
The microprocessor or microcontroller connected to Port A controls all
operations of the BiFIFO. Thus, all Port A interface pins are inputs driven
by the controlling processor. Port B can be programmed to interface
either with a second processor or a peripheral device. When Port B is
programmed in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device is connected
to the BiFIFO, Port B is programmed to peripheral interface mode and the
interface pins are outputs.
18- TO 18-BIT CONFIGURATIONS
A single BiFIFO can be configured to connect an 18-bit processor to
another 18-bit processor or an 18-bit peripheral. The upper BiFIFO shown
in each of the Figures 1 and 2 can be used in 18- to 18-bit configurations for
processor and peripheral interface modes respectively.
36- TO 36-BIT CONFIGURATIONS
In a 36- to 36-bit configuration, two BiFIFOs operate in parallel. Both
BiFIFOs are programmed simultaneously, 18 data bits to each device.
Figures 1 and 2 show multiple BiFIFOs configured for processor and
peripheral interface modes respectively.
PROCESSOR INTERFACE MODE
When a microprocessor or microcontroller is connected to Port B, all
BiFIFOs in the configuration must be programmed to processor interface
mode. In this mode, all Port B interface controls are inputs. Both REQ and
CLK pins should be pulled LOW to ensure that the setup and hold time
requirements for these pins are met during reset. Figure 1 shows the
BiFIFO in processor interface mode.
PERIPHERAL INTERFACE MODE
If Port B is connected to a peripheral controller, all BiFIFOs in the
configuration must be programmed in peripheral interface mode. In this
mode, all the Port B interface pins are all outputs. To assure fixed high
states for
R
B
and
W
B
before they are programmed into an output, these
two pins should be pulled up to V
CC
with 10K resistors. Of course, only
one set of Port B interface pins should be used to control a single
peripheral device, while the other interface pins are all ignored. Figure 2
shows a BiFIFO configuration connected to a peripheral.
IDT
BiFIFO
Cntl A
Cntl B
ACK
REQ
CLK
Data A Data B
Control
Logic
Address
Control
Data
Control
Logic
Processor
A
Processor
B
Control
36-bit bus
36-bit bus
36
IDT
BiFIFO
Cntl A
Cntl B
ACK
REQ
CLK
18
Data
36
RAM
RAM
Data A Data B
18
2668 drw 04
NOTE:
1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that
Cntl A
refers to
CS
A,
A
1
, A
0
, R/W
A,
and
DS
A;
Cntl B
refers to R/W
B
and
DS
B
or
R
B
and
W
B.
Figure 1. 36-Bit Processor to 36-Bit Processor Configuration
5
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