74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 7 — 11 April 2013
Product data sheet
1. General description
The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs
(nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC125AD
74LVC125ADB
Name
Description
plastic small outline package; 14 leads; body width
3.9 mm; body thickness 1.47 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
40 C
to +125
C
SO14
40 C
to +125
C
SSOP14
74LVC125APW
40 C
to +125
C
TSSOP14
74LVC125ABQ
40 C
to +125
C
DHVQFN14
plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
2
1
5
4
9
10
12
13
1A
1OE
2A
2OE
1Y
3
2
1
3
2Y
6
1
5
EN1
6
4
3A
3OE
4A
4OE
mna228
3Y
8
9
8
10
4Y
11
12
11
13
nA
nY
nOE
mna229
mna227
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74LVC125A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 April 2013
2 of 16
NXP Semiconductors
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
5. Pinning information
5.1 Pinning
1OE
2
3
4
5
6
7
GND
3Y
8
1
1A
1Y
2OE
2A
2Y
GND
2
3
4
5
6
7
001aad045
1OE
1
14 V
CC
13 4OE
12 4A
terminal 1
index area
1A
1Y
2OE
2A
14 V
CC
13 4OE
12 4A
11 4Y
10 3OE
9
3A
125
11 4Y
10 3OE
9
8
3A
3Y
125
GND
(1)
2Y
001aad046
Transparent top view
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to GND.
Fig 4.
Pin configuration for SO14 and (T)SSOP14
Fig 5.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1Y, 2Y, 3Y, 4Y
GND
V
CC
Pin description
Pin
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
data enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
1OE, 2OE, 3OE, 4OE 1, 4, 10, 13
6. Functional description
Table 3.
Inputs
nOE
L
L
H
[1]
Function selection
[1]
Output
nA
L
H
X
nY
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
74LVC125A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 April 2013
3 of 16
NXP Semiconductors
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
500
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW-state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
C
derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
output HIGH or LOW state
output 3-state
Conditions
Min
1.65
1.2
0
0
0
40
0
0
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
74LVC125A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 April 2013
4 of 16
NXP Semiconductors
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level input V
CC
= 1.2 V
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
OZ
I
OFF
I
CC
I
CC
C
I
input leakage
current
OFF-state
output current
V
CC
= 3.6 V; V
I
= 5.5 V or GND
V
I
= V
IH
or V
IL
; V
CC
= 3.6 V;
V
O
= 5.5 V or GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.1
5
4.0
0.2
0.45
0.6
0.4
0.55
5
5
10
10
500
-
-
-
-
-
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
20
20
40
5000
-
V
V
V
V
V
A
A
A
A
A
pF
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
40 C
to +85
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.12
0.35
V
CC
0.7
0.8
40 C
to +125
C
Min
1.08
0.65
V
CC
1.7
2.0
-
-
-
-
Max
-
-
-
-
0.12
0.7
0.8
V
V
V
V
V
V
V
Unit
0.35
V
CC
V
power-off
V
CC
= 0.0 V; V
I
or V
O
= 5.5 V
leakage current
supply current
additional
supply current
input
capacitance
V
CC
= 3.6 V; V
I
= V
CC
or GND;
I
O
= 0 A
per input pin; V
I
= V
CC
0.6 V;
I
O
= 0 A; V
CC
= 2.7 V to 3.6 V
V
CC
= 0 V to 3.6 V;
V
I
= GND to V
CC
[1]
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25
C.
74LVC125A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 11 April 2013
5 of 16
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