74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
Rev. 6 — 19 December 2011
Product data sheet
1. General description
74HC423; 74HCT423 are high-speed Si-gate CMOS devices that are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC423; 74HCT423 dual retriggerable monostable multivibrator with reset has two
methods of output pulse width control.
1. The minimum pulse width is essentially determined by the selection of an external
resistor (R
EXT
) and capacitor (C
EXT
), see
Section 12.1.
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. When nRD is LOW, it forces the nQ output LOW, the nQ output
HIGH and also inhibits the triggering.
Figure 10
and
Figure 11
illustrate pulse control
by reset.
The nA and nB inputs’ Schmitt trigger action makes them highly tolerant to slower input
rise and fall times.
The 74HC423; 74HCT423 are identical to the 74HC123; 74HCT123 except that they
cannot be triggered via the reset input.
2. Features and benefits
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt-trigger action on all inputs except for the reset input
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Ordering information
Temperature range Name
74HC423N
74HCT423N
74HC423D
74HCT423D
74HC423BQ
74HCT423BQ
74HCT423DB
40 C
to +125
C
74HCT423PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
40 C
to +125
C
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number Package
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT338-1
SOT403-1
4. Functional diagram
14
15
S
Q
1A
1
T
2
RD
3
6
7
S
Q
2A
9
T
10
RD
11
001aah796
1CEXT
1REXT/CEXT
13
1Q
Q
4
1Q
1B
1RD
2CEXT
2REXT/CEXT
5
2Q
Q
12
2Q
2B
2RD
Fig 1.
Functional Diagram
74HC_HCT423
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 19 December 2011
2 of 24
NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
14
15
1
1CEXT 14
2CEXT
6
3
1REXT/CEXT 15
2REXT/CEXT
S
Q
1 1A
9 2A
2 1B
10 2B
3 1RD
11 2RD
T
Q
RD
1Q
4
9
10
11
001aah797
CX
RCX
&
4
R
13
2
7
6
7
1Q 13
2Q 5
CX
RCX
&
12
R
001aah798
5
2Q 12
Fig 2.
Logic symbol
Fig 3.
IEC Logic symbol
REXT/CEXT
V
CC
RD
R
CL
V
CC
V
CC
R
CL
Q
Q
CL
A
CL
CL
B
001aah799
Fig 4.
Logic diagram
74HC_HCT423
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 19 December 2011
3 of 24
NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
74HC423
74HCT423
terminal 1
index area
1B
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
9
001aah785
74HC423
74HCT423
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
2A
9
V
CC(1)
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
1
1A
2A
001aah784
Transparent top view
(1) The die substrate is attached to this pad using a
conductive die attach material. It cannot be used as
supply pin or input
Fig 5.
Pin configuration DIP16, SO16 and (T)SSOP16
Fig 6.
Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
1A, 2A
1B, 2B
1RD, 2RD
1Q, 2Q
GND
1Q, 2Q
1CEXT, 2CEXT
1REXT/CEXT, 2REXT/CEXT
V
CC
Pin description
Pin
1, 9
2, 10
3, 11
4, 12
8
13, 5
14, 6
15, 7
16
Description
trigger input (negative edge triggered)
trigger input (positive edge triggered)
direct reset (active LOW)
output (active LOW)
ground (0 V)
output (active HIGH)
external capacitor connection
external resistor/capacitor connection
supply voltage
74HC_HCT423
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 19 December 2011
4 of 24
NXP Semiconductors
74HC423; 74HCT423
Dual retriggerable monostable multivibrator with reset
6. Functional description
Table 3.
Input
nRD
L
X
X
H
H
[1]
Function table
[1]
Output
nA
X
H
X
L
nB
X
X
L
H
nQ
L
L
[2]
L
[2]
nQ
H
H
[2]
H
[2]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition;
= one HIGH level output pulse;
= one LOW level output pulse.
[2]
If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
[1]
[2]
[3]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7
20
20
25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP16 packages: above 70
C
the value of P
tot
derates linearly at 12 mW/K.
For SO16 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K;
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K;
For DHVQFN16 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
74HC_HCT423
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 19 December 2011
5 of 24
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
