PL607041
ClockWorks
®
PCIe Quad Outputs
Ultra-Low Jitter, HCSL Frequency
Synthesizer
General Description
The PL607041 is a member of the ClockWorks family of
devices from Micrel and provides an extremely low-noise
Spread-Spectrum clock for PCI Express requirements.
The device operates from a 3.3V or 2.5V power supply
and synthesizes four HCSL output clocks at 25MHz,
100MHz, 125MHz, and 200MHz. The PL607041 accepts a
25MHz crystal.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
®
Features
25MHz fundamental crystal or reference input
Generates four HCSL clock outputs at 25MHz, 100MHz,
125MHz, and 200MHz
Spread spectrum for EMI reduction
2.5V or 3.3V operating range
Typical phase jitter @ 100MHz (1.5MHz to 10MHz):
320fs
Compliant with PCI Express Gen1, Gen2, and Gen3
Industrial temperature range (–40°C to +85°C)
RoHS and PFOS compliant
Available in 24-pin 4mm × 4mm QFN package
Applications
Servers
Storage systems
Switches and routers
Gigabit Ethernet
Set-top boxes/DVRs
Block Diagram
ClockWorks is a registered trademark of Micrel, Inc.
Ripple Blocker is a trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
April 1, 2014
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL607041
Ordering Information
(1)
Part Number
PL607041UMG
PL607041UMG TR
Note:
1. Devices are RoHS and PFOS compliant.
Marking
PL607
041
PL607
041
Shipping
Tube
Tape and Reel
Junction Temperature
Range
–40° to +85°C
–40° to +85°C
Package
24-Pin QFN
24-Pin QFN
Pin Configuration
24-Pin QFN
(Top View)
Pin Description
Pin Number
17, 18
19, 20
23, 24
1, 2
9
16
7, 15
5, 11, 13
6, 8
14, 4
22
21
12
3, 10
Pin Name
/Q0, Q0
/Q1, Q1
/Q2, Q2
/Q3, Q3
VDDO2
VDDO1
VDD
VSS
S0, S1
SS0, SS1
XIN/FIN
XOUT
OE
TEST
Pin Type
O, (DIF)
O, (DIF)
PWR
PWR
PWR
PWR
I
I
I, (SE)
O, (SE)
I, (SE)
I
LVCMOS
LVCMOS
Crystal
Crystal
LVCMOS
Pin Level
HCSL
HCSL
Pin Function
Differential Clock Outputs pins.
Differential Clock Outputs pins.
Power Supply.
Power Supply.
Core Power Supply.
Power Supply Ground.
Frequency Select for 25MHz, 100MHz, 125MHz, and
200MHz. Each pin has a 45kΩ pull-up.
Spread Spectrum Select pins. Each pin has a 60kΩ pull-
up.
Crystal or Reference Input, no load caps needed (see
Figure 5).
Crystal Output, no load caps needed (see
Figure 5).
Output Enable/Disable.
Factory test pins. Keep these pins floating.
April 1, 2014
2
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL607041
EMI Reduction
The Spread Spectrum modulation causes the emission of
spectral components in the clock signal to be reduced. The
spectrum plot on the right shows measurement results with
the two spread settings versus no spread. This plot is
looking at the 11th harmonic in a 100MHz clock, at
1.1GHz. The scale is normalized to the strength of this
spur without spread. The plot shows about 21dB reduction
for -0.25% spread magnitude and 24dB for -0.50% spread
magnitude.
The plot also shows how the frequency spreading is
happening downwards.
April 1, 2014
3
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL607041
Absolute Maximum Ratings
(2)
Supply Voltage (V
DD,
V
DDO1/2
) ....................................... +4.6V
Input Voltage (V
IN
) ............................... –0.50V to V
DD
+ 0.5V
Lead Temperature (soldering, 20s) ............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts)......................... –65°C to +150°C
Operating Ratings
(3)
Supply Voltage (V
IN
) ............................. +2.375V to +3.465V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
(4)
Junction Thermal Resistance
QFN (
JA
) ........................................................... 50°C/W
QFN (
JB
)........................................................... 30°C/W
Electrical Characteristics
(5)
V
DD
= V
DDO1/2
= 3.3V ±5% or 2.5V ±5%
V
DD
= 3.3V ±5%, V
DDO1/2
= 3.3V ±5% or 2.5V ±5%
T
A
= –40°C to +85°C
Symbol
V
DD
,
V
DDO1/2
V
DD
,
V
DDO1/2
I
DD
Parameter
2.5V operating voltage
3.3V operating voltage
Supply current V
DD
+ V
DDO
Outputs 50Ω to V
SS
Condition
Min.
2.375
3.135
Typ.
2.5
3.3
150
Max.
2.625
3.465
185
Units
V
V
mA
HCSL DC Electrical Characteristics
(5)
V
DD
= V
DDO1/2
= 3.3V ±5% or 2.5V ±5%
V
DD
= 3.3V ±5%, V
DDO1/2
= 3.3V ±5% or 2.5V ±5%
T
A
= –40°C to +85°C. RL = 50Ω to V
SS
Symbol
V
OH
V
OL
V
CROSS
Parameter
Output High Voltage
Output Low Voltage
Crossing Point Voltage
Condition
Min.
660
–150
250
Typ.
700
0
350
Max.
850
27
550
Units
mV
mV
mV
LVCMOS (S0, S1) Electrical Characteristics
(5)
V
DD
= 3.3V ±5%, or 2.5V ±5%, T
A
= –40°C to +85°C.
Symbol
V
IH
V
IL
I
IH
I
IL
Notes:
2. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3. The device is not guaranteed to function outside its operating ratings.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
5. The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Condition
Min.
2.0
–0.3
Typ.
Max.
V
DD
+
0.3
0.8
150
Units
V
V
µA
µA
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
–150
April 1, 2014
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Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
Micrel, Inc.
PL607041
Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
(ESR)
Shunt Capacitor, C0
Correlation Drive Level
1
10
Condition
15pF load capacitance
Min.
Typ.
Max.
Units
Fundamental, Parallel Resonant
25
50
7
100
MHz
Ω
pF
µW
AC Electrical Characteristics
(6,
7)
V
DD
= V
DDO1/2
= 3.3V ±5% or 2.5V ±5%
V
DD
= 3.3V ±5%, V
DDO1/2
= 3.3V ±5% or 2.5V ±5%
T
A
= –40°C to +85°C. RL = 50Ω to V
SS
Symbol
Parameter
Condition
Min.
Typ.
25
100
125
200
25
25
Internally AC-coupled
20% - 80%
0.9
150
48
Note 7
300
50
V
DD
450
52
45
20
(8)
Max.
Units
F
OUT
Output Frequency
MHz
F
REF
FIN
FIN
T
R
/T
F
ODC
T
SKEW
T
LOCK
Crystal Input Frequency
Reference Input Frequency
FIN Signal Amplitude
HCSL Output Rise/Fall Time
Output Duty Cycle
Output-to-Output Skew
PLL Lock Time
RMS Phase Jitter
100MHz
Integration Range (1.5MHz – 10MHz)
MHz
MHz
V
PP
ps
%
ps
ms
fs
30
ps,
peak
320
T
jit
(Ø)
Cycle-to-Cycle Jitter
Notes:
6. All phase noise measurements were taken with an Agilent 5052B phase noise system.
7. Defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differential crossing points.
8. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
Spread Spectrum Characteristics
Parameter
Modulation Rate
(9)
Condition
Min.
Typ.
31.6
Max.
Units
kHz
Modulation Magnitude
Notes:
(10)
Setting is -0.25%
Setting is -0.50%
-0.073 to -0.265
-0.136 to -0.383
0 to -0.250
0 to -0.500
+0.031 to -0.375
+0.078 to -0.589
%
%
9. The modulation rate is created from the crystal frequency, divided by 792.
10. The typical modulation makes the output frequency sweep between the target frequency (0%) and the down-spread value (-0.25% or -0.5%). There
is process variation on the modulation magnitude and the smallest and largest possible modulation magnitude sweep ranges are listed in the table.
April 1, 2014
5
Revision 1.2
tcghelp@micrel.com
or (408) 955-1690
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