HIP6004D
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN4855
Rev 3.00
July 13, 2005
Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
The HIP6004D provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004D integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004D includes a fully TTL-
compatible 5-input digital-to-analog converter (DAC) that
adjusts the output voltage from 1.1V
DC
to 1.85V
DC
in 25mV
increments steps. The precision reference and voltage-
mode regulator hold the selected output voltage to within
1%
over temperature and line voltage variations.
The HIP6004D provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/s slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The HIP6004D monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within
10%.
The HIP6004D
protects against over-current and overvoltage conditions by
inhibiting PWM operation. Additional built-in overvoltage
protection triggers an external SCR to crowbar the input
supply. The HIP6004D monitors the current by using the
r
DS(ON)
of the upper MOSFET which eliminates the need for
a current sensing resistor.
Features
• Drives Two N-Channel MOSFETs
• Operates from +5V or +12V Input
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
-
1%
Over Line Voltage and Temperature
• TTL-Compatible 5-Bit Digital-to-Analog Output
Voltage Selection
- 25mV Binary Steps . . . . . . . . . 1.100V
DC
to 1.850V
DC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER
HIP6004DCB
HIP6004DCBZ
(See Note)
HIP6004DCR
HIP6004DCRZ
(See Note)
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
20 Ld SOIC
20 Ld SOIC
(Pb-free)
20 Ld 5x5 QFN
20 Ld 5x5 QFN
(Pb-free)
PKG.
DWG. #
M20.3
M20.3
L20.5x5
L20.5x5
Applications
• Power Supply for K7™, and Other Microprocessors
• High-Power DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
FN4855 Rev 3.00
July 13, 2005
Page 1 of 14
HIP6004D
Absolute Maximum Ratings
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Boot Voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . . . . . . . . . . . . . .+15V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance
JA
(
o
C/W)
JC
(
o
C/W)
Operating Conditions
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V
10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
SOIC Package (Note 1) . . . . . . . . . . . .
65
NA
QFN Package (Notes 2, 3). . . . . . . . . .
33
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
POWER-ON RESET
Rising V
CC
Threshold
Falling V
CC
Threshold
Rising V
OCSET
Threshold
OSCILLATOR
Free Running Frequency
Total Variation
Ramp Amplitude
REFERENCE AND DAC
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
UGATE and LGATE Open
-
5
-
mA
V
OCSET
= 4.5V
V
OCSET
= 4.5V
-
8.2
-
-
-
1.26
10.4
-
-
V
V
V
RT = OPEN
6k < RT to GND < 200k
V
OSC
RT = Open
185
-15
-
200
-
1.9
215
+15
-
kHz
%
V
P-P
DAC (VID0-VID4) Input Low Voltage
DAC (VID0-VID4) Input High Voltage
DACOUT Voltage Accuracy
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
PROTECTION
Over-Voltage Trip (VSEN/DACOUT)
OCSET Current Source
OVP Sourcing Current
Soft Start Current
I
OCSET
I
OVP
I
SS
V
OCSET
= 4.5V
DC
V
SEN
= 5.5V, V
OVP
= 0V
I
UGATE
R
UGATE
I
LGATE
R
LGATE
V
BOOT
- V
PHASE
= 12V, V
UGATE
= 6V
I
LGATE
= 0.3A
V
CC
= 12V, V
LGATE
= 6V
I
LGATE
= 0.3A
GBWP
SR
COMP = 10pF
-
2.0
-1.0
-
-
-
0.8
-
+1.0
V
V
%
-
-
-
88
15
6
-
-
-
dB
MHz
V/s
350
-
300
-
500
5.5
450
3.5
-
10
-
6.5
mA
mA
-
170
60
-
115
200
-
10
120
230
-
-
%
µA
mA
µA
FN4855 Rev 3.00
July 13, 2005
Page 4 of 14
HIP6004D
Electrical Specifications
PARAMETER
POWER GOOD
Upper Threshold (VSEN/DACOUT)
Lower Threshold (VSEN/DACOUT)
Hysteresis (VSEN/DACOUT)
PGOOD Voltage Low
V
PGOOD
VSEN Rising
VSEN Falling
Upper and Lower Threshold
I
PGOOD
= -5mA
106
89
-
-
-
-
2
0.5
111
94
-
-
%
%
%
V
Recommended Operating Conditions, Unless Otherwise Noted
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Typical Performance Curves
80
70
1000
RESISTANCE (k)
R
T
PULLUP
TO +12V
I
CC
(mA)
60
50
40
30
10
R
T
PULLDOWN TO V
SS
20
10
10
100
SWITCHING FREQUENCY (kHz)
1000
0
100
200
300
400
500
600
C
GATE
= 10pF
C
GATE
= 1000pF
C
UPPER
= C
LOWER
= C
GATE
C
GATE
= 3300pF
100
700
800
900
1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R
T
RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
Functional Pin Descriptions
VSEN
OCSET
SS
VID0
VID1
VID2
VID3
VID4
COMP
1
2
3
4
5
6
7
8
9
20 RT
19 OVP
18 VCC
17 LGATE
16 PGND
15 BOOT
14 UGATE
13 PHASE
12 PGOOD
11 GND
the converter over-current (OC) trip point according to the
following equation:
I
OCSET
x R
OCSET
-
I
PEAK
= ----------------------------------------------------
r
DS
ON
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
FB 10
VID0-4 (Pins 4-8)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the all combinations of DAC inputs.
V
SEN
(Pin 1)
This pin is connected to the converter’s output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
OCSET (Pin 2)
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET. R
OCSET
, an internal 200µA current source
(I
OCS
), and the upper MOSFET on-resistance (r
DS(ON)
) set
COMP (Pin 9) and FB (Pin 10)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
FN4855 Rev 3.00
July 13, 2005
Page 5 of 14
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