CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
High Level Clock Input
Low Level Clock Input
Output High Voltage
SYMBOL
V
IH
V
IL
V
IHC
V
ILC
V
OH
V
OL
I
L
I
O
I
CCSB
CONDITIONS
V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
V
CC
= 4.5V
I
OH
= -400µA,
V
CC
= 4.5V (Note 2)
I
OL
= +2.0mA,
V
CC
= 4.5V (Note 2)
V
IN
= V
CC
or GND,
V
CC
= 5.5V
V
OUT
= V
CC
or GND,
V
CC
= 5.5V
V
IN
= V
CC
or GND,
V
CC
= 5.5V,
Outputs Open
f = 25.6MHz,
V
IN
= V
CC
or GND
V
CC
= 5.5V (Note 3)
(Notes 4, 5)
GROUP A
SUBGROUP
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
TEMP (
o
C)
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
-55
≤
T
A
≤
125
MIN
2.2
-
3.0
-
2.6
MAX
-
0.8
-
0.8
-
UNITS
V
V
V
V
V
Output Low Voltage
1, 2, 3
-
0.4
V
µA
µA
µA
Input Leakage Current
1, 2, 3
-10
10
I/O Leakage Current
1, 2, 3
-10
10
Standby Supply Current
1, 2, 3
-
500
Operating Power Supply Cur-
rent
I
CCOP
1, 2, 3
-55
≤
T
A
≤
125
-
308
mA
Functional Test
NOTES:
FT
7, 8
-55
≤
T
A
≤
125
-
-
-
2. Interchanging of force and sense conditions is permitted.
3. Power supply current is proportional to operating frequency. Typical rating for I
CCOP
is 12mA/MHz. Maximum junction temperature must be
considered when operating part at high clock frequencies.
4. Tested as follows: f = 1MHz, V
IH
= 2.6V, V
IL
= 0.4V, V
OH
≥
1.5V, V
OL
≤
1.5V, V
IHC
= 3.4V and V
ILC
= 0.4V.
5. Loading is as specified in the test load circuit with C
L
= 40pF.
4
HSP48410/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
CC
= 5.0V
±10%,
T
A
= -55
o
C to 125
o
C (Note 1)
-33 (33MHz)
PARAMETER
Clock Period
Clock Low
Clock High
DIN Setup
DIN 0-23 Hold
Clock to DIO 0-23 Valid
FC Pulse Width
FCT 0-2 Setup to LD
FCT 0-2 Hold from LD
START Setup to CLK
START Hold from CLK
PIN 0-9 Setup Time
PIN 0-9 Hold Time
LD Pulse Width
LD Setup to START
WR Low
WR High
Address Setup
Address Hold
DIO Setup to WR
DIO Hold from WR
RD Low
RD High
RD Low to DIO Valid
Output Enable Time
Read/Write Cycle Time
NOTES:
6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)
= 2.0V, (all others) = 1.5V. Output load circuit with C
L
= 40pF. Output transition measured at V
OH
≥
1.5V and V
OL
≥
1.5V.
7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.
8. Transition is measured at
±200
mV from steady state voltage with loading as specified in test load circuit with C
FPGA/CPLD
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