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74HC373
Octal 3−State Non−Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The 74HC373 is identical in pinout to the LS373. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the non−inverting version of the HC533A.
Features
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MARKING
DIAGRAM
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
1
HC
373
ALYW
G
G
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
This is a Pb−Free Device
HC373
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 0
1
Publication Order Number:
74HC373/D
74HC373
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
D0
D1
NONINVERTING
OUTPUTS
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LATCH
ENABLE
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
LATCH ENABLE
OUTPUT ENABLE
11
1
FUNCTION TABLE
Inputs
Output
Enable
Latch
Enable
D
H
L
X
X
Output
Q
H
L
No Change
Z
L
H
L
H
L
L
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
Value
46.5
1.5
5.0
0.0075
Units
ea
ns
mW
pJ
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2
74HC373
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP Package)
TSSOP Package†
DC Output Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±35
±75
450
– 65 to + 150
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
V
CC
+ 125
1000
500
400
Unit
V
V
_C
ns
ORDERING INFORMATION
Device
74HC373DTR2G
Package
TSSOP−20*
Shipping
†
2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
74HC373
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
– 55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
V
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
mA
mA
V
in
= V
CC
or GND
6.0
4.0
40
40
mA
I
out
= 0
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
I
CC
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4
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