FINAL
COM’L: -5/7/10/12/15
IND: -7/10/12/14/18
MACH
®
111-5/7/10/12/15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x
44 Pins in PLCC and TQFP
x
32 Macrocells
x
5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
x
182 MHz f
CNT
x
32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
x
x
x
x
x
x
x
x
32 Flip-flops; 4 clock choices
2 “PALCE26V16” blocks
SpeedLocking™ for guaranteed fixed timing
Bus-Friendly™ Inputs and I/Os
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12)
Programmable power-down mode
Safe for mixed supply voltage system designs
Pin-compatible with the MACH211
GENERAL DESCRIPTION
The MACH111 is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This
device has approximately three times the logic macrocell capability of the popular PALCE22V10
without loss of speed.
The MACH111 consists of two PAL
®
blocks interconnected by a programmable switch matrix.
The two PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays
and programmable macrocells, which can be programmed as high speed or low power. The
switch matrix connects the PAL blocks to each other and to all input pins, providing a high
degree of connectivity between the fully connected PAL blocks. This allows designs to be placed
and routed efficiently.
The MACH111 macrocell provides either registered or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the register can be configured as D-type or T-
type to help reduce the number of product terms. The register type decision can be made by
the designer or by the software. All macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the macrocell can be used, which frees up
the I/O pin for use as an input.
Vantis offers software design support for MACH devices through its own development system
and device fitters integrated into third-party CAE tools. Platform support extends across PCs,
Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95
and NT, SunOS and Solaris, and HPUX.
Publication#
20420
Amendment/+1
Rev:
B
Issue Date:
June 1998
MACHXL
®
software is a complete development system for the PC, supporting Vantis' MACH
devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and
truth tables. Functional simulation and static timing analysis are also included in this easy-to-
use system. This development system includes high-performance device fitters for all MACH
devices.
The same fitter technology included in MACHXL software is seamlessly incorporated into third-party
tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC.
Interface kits and MACHXL configurations are also available to support design entry and verification
with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology.
These MACHXL configurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC files for
MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output files for
design simulation.
Vantis offers in-system programming support for MACH devices through its MACHPRO
®
software enabling MACH device programmability through JTAG compliant ports and easy-to-use
PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad
and Teradyne testers to program MACH devices or test them for connectivity.
All MACH devices are supported by industry standard programmers available from a number of
vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O
Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.
2
MACH111-5/7/10/12/15
stm32/stm8
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