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FINAL

COM’L: -5/7/10/12/15

IND: -7/10/12/14/18

MACH

®

111-5/7/10/12/15

High-Performance EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

x

44 Pins in PLCC and TQFP

x

32 Macrocells

x

5 ns t

PD

Commercial, 7.5 ns t

PD

Industrial

x

182 MHz f

CNT

x

32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

x

32 Flip-ﬂops; 4 clock choices

2 “PALCE26V16” blocks

SpeedLocking™ for guaranteed ﬁxed timing

Bus-Friendly™ Inputs and I/Os

Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12)

Programmable power-down mode

Safe for mixed supply voltage system designs

Pin-compatible with the MACH211

GENERAL DESCRIPTION

The MACH111 is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This

device has approximately three times the logic macrocell capability of the popular PALCE22V10

without loss of speed.

The MACH111 consists of two PAL

®

blocks interconnected by a programmable switch matrix.

The two PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays

and programmable macrocells, which can be programmed as high speed or low power. The

switch matrix connects the PAL blocks to each other and to all input pins, providing a high

degree of connectivity between the fully connected PAL blocks. This allows designs to be placed

and routed efﬁciently.

The MACH111 macrocell provides either registered or combinatorial outputs with programmable

polarity. If a registered conﬁguration is chosen, the register can be conﬁgured as D-type or T-

type to help reduce the number of product terms. The register type decision can be made by

the designer or by the software. All macrocells can be connected to an I/O cell. If a buried

macrocell is desired, the internal feedback path from the macrocell can be used, which frees up

the I/O pin for use as an input.

Vantis offers software design support for MACH devices through its own development system

and device ﬁtters integrated into third-party CAE tools. Platform support extends across PCs,

Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95

and NT, SunOS and Solaris, and HPUX.

Publication#

20420

Amendment/+1

Rev:

B

Issue Date:

June 1998

MACHXL

®

software is a complete development system for the PC, supporting Vantis' MACH

devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and

truth tables. Functional simulation and static timing analysis are also included in this easy-to-

use system. This development system includes high-performance device ﬁtters for all MACH

devices.

The same ﬁtter technology included in MACHXL software is seamlessly incorporated into third-party

tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC.

Interface kits and MACHXL conﬁgurations are also available to support design entry and veriﬁcation

with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology.

These MACHXL conﬁgurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC ﬁles for

MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output ﬁles for

design simulation.

Vantis offers in-system programming support for MACH devices through its MACHPRO

®

software enabling MACH device programmability through JTAG compliant ports and easy-to-use

PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad

and Teradyne testers to program MACH devices or test them for connectivity.

All MACH devices are supported by industry standard programmers available from a number of

vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O

Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.

2

MACH111-5/7/10/12/15

BLOCK DIAGRAM

Block A

I/O

0

– I/O

15

I

0

-I

1

/CLK

0

I

3

-I

4

/CLK

2

16

I/O Cells

16

4

Macrocells

16

4

2

OE

52 x 70

AND Logic Array

and

Logic Allocator

26

4

Switch Matrix

26

52 x 70

AND Logic Array

and

Logic Allocator

OE

4

16

2

16

2

4

Macrocells

16

I/O Cells

I/O

16

– I/O

31

Block B

CLK

3

/I

5

CLK

1

/I

2

20420B-1

MACH111-5/7/10/12/15

3

CONNECTION DIAGRAM

Top View

44-Pin PLCC

I/O31

I/O30

I/O29

6

I/O5

I/O6

I/O7

I0

Block A

CLK0/I1

GND

CLK1/I2

I/O8

I/O9

I/O10

I/O11

7

8

9

10

11

12

13

14

15

16

17

5 4

3 2

1 44 43 42 41 40

39

38

37

36

35

34

33

32

31

30

29

I/O27

I/O26

I/O25

I/O24

Block B

CLK3/I5

GND

CLK2/I4

I3

I/O23

I/O22

I/O21

18 19 20 21 22 23 24 25 26 27 28

I/O12

I/O13

I/O14

I/O15

GND

I/O16

I/O17

I/O18

I/O19

I/O20

VCC

I/O28

GND

I/O4

I/O3

I/O2

I/O1

I/O0

VCC

20420B-2

Note:

Pin-compatible with the MACH211SP and MACH211.

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

I/O

V

CC

= Input

= Input/Output

= Supply Voltage

4

MACH111-5/7/10/12/15

CONNECTION DIAGRAM

Top View

44-Pin TQFP

I/O5

I/O6

I/O7

I0

CLK0/I1

GND

CLK1/I2

I/O8

I/O9

I/O10

I/O11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

I/O4

I/O3

I/O2

I/O1

I/O0

GND

VCC

I/O31

I/O30

I/O29

I/O28

I/O27

I/O26

I/O25

I/O24

CLK3/I5

GND

CLK2/I4

I3

I/O23

I/O22

I/O21

Block B

Block A

I/O12

I/O13

I/O14

I/O15

VCC

GND

I/O16

I/O17

I/O18

I/O19

I/O20

20420B-3

Note:

Pin-compatible with the MACH211SP.

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

I/O

V

CC

= Input

= Input/Output

= Supply Voltage

MACH111-5/7/10/12/15

5

MACH111-5

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