Semiconductor
HI2559, CXD2559
DE
RN
D FO
EW
IG
DES
NS
October 1997
Features
EN
OMM
EC
OT R
N
1-Bit D/A Converter For Audio Application
Description
The HI2559, CXD2559 is a 1-bit stereo D/A converter featur-
ing a 2nd-order
∆∑
system noise shaper. This good cost per-
formance LSI has functions such as digital attenuator and
digital de-emphasis and others.
• Two-Channel D/A Converter and Oversampling Digital
Filter Into a Single Chip
• Distortion . . . . . . . . . . . . . . . . . . . . . . . . 0.012% or Less
• S/N Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 96dB or More
• Master Clock. . . . . . . . . . . . . . . . . . . . . . 384F
S
or 256F
S
Ordering Information
PART
NUMBER
HI2559JCQ
CXD2559Q
TEMP.
RANGE (
o
C)
-20 to 75
-20 to 75
PACKAGE
32 Ld MPQF
32 Ld MPQF
PKG. NO.
Q32.7x7-S
Q32.7x7-S
Applications
• CD Player and CD-ROM Player, etc.
Functions
• Data Can Be Input at Rate of 1 x F
S
with a Built-In Digital
Filter
• The 24-/32-Slot Serial Data Interface Enables
Independent Selection of Data Frontward Trunca-
tion/Rearward Truncation and MSB First/LSB First
• Two Channels Can Be Attenuated Independently in 255
Steps
• The Output From Two Channels (L/R/L + R/Mute) Can
Be Selected Independently
• Digital Emphasis
Pinout
HI2559, CXD2559
(MQFP)
TOP VIEW
AOUT2+
AV
SS3
XV
SS
XTLI
XTLO
XV
DD
AV
SS2
AOUT1+
AV
DD0
AOUT2-
AV
SS0
DV
DD0
TEST
CLR
MASL
DV
SS0
3231 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
18
7
17
8
9 10 11 12 13 14 15 16
AV
DD1
AOUT1-
AV
SS1
DV
SS1
XCLK
DASL0
DASL1
DV
DD1
LRCK
BCK
SIN
MLSL
ATT
SHIFT
LATCH
WO
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1997
File Number
4120.1
4-1
HI2559, CXD2559
Block Diagram
XTLI
XTLO
XCLK
CLOCK GENERATOR
TIMING CIRCUIT
AOUT1 (+)
DAC1
LRCK
BCK
SIN
MASL
MLSL
S
P
DAC2
AOUT2 (-)
DIGITAL
FILTER
(OVER SAMPLING)
AOUT1 (-)
AOUT2 (+)
ATT
SHIFT
LATCH
HOST
COMPUTER
I/F
ROM
ATT1
ATT2
RAM
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
SYMBOL
AV
DD0
AOUT2(–)
ADV
SS0
DV
DD0
TEST
CLR
MASL
I/O
-
O
-
-
I
I
I
DESCRIPTION
Analog power supply for Channel 2 output.
Analog reversed phase output for Channel 2.
Analog GND for Channel 2 output.
Digital power supply.
IC measurement. Fixed to Low.
System clear input. Cleared when low. Equipped with a pull-up resistor.
Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the
serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low.
Equipped with a pulldown resistor.
Digital GND.
Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data
when low.
Serial bit transfer clock 48 F
S
or 64 F
S
in serial IN. The serial input data is retrieved at the
rising edge.
Two channels per sampling serial data input. Data format is represented by 2’s comple-
ments, and consists of 24-bit or 32-bit slots.
Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSB-
first when High; LSB-first when Low. Equipped with a pull-up resistor.
8
9
10
11
12
DV
SS0
LRCK
BCK
SIN
MLSL
-
I
I
I
I
4-2
HI2559, CXD2559
Pin Descriptions
PIN NO.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ATT
SHIFT
LATCH
WO
DV
DD1
DASL1
DASL0
XCLK
DV
SS1
AV
SS1
AOUT1 (-)
AV
DD1
AOUT1 (+)
AV
SS2
XV
DD
XTLO
XTLI
XV
SS
AV
SS3
AOUT2 (+)
(Continued)
I/O
I
I
I
I
-
I
I
O
-
-
O
I
O
-
-
O
I
-
-
O
DESCRIPTION
Data input of the microcomputer interface. Attenuation data, output selection setting value,
and de-emphasis on/off data re-input in serial mode.
Shift clock input of the microcomputer interface.
Latch input of the microcomputer interface. Latched at the rising edge.
Synchronization window control. Window open when Low (forced synchronization).
Digital power supply.
IC measurement. Fixed to Low.
IC measurement. Fixed High.
Inversion output of the clock input from XTLI (Pin 1).
Digital GND.
Analog GND for Channel 1 output.
Analog reversed phase output for Channel 1.
Analog power supply for Channel 1 output.
Analog positive phase output for Channel 1.
Analog GND for Channel 1 output.
Digital power supply for the master clock.
Crystal oscillator output. Connects the master clock 256 F
S
or 384 F
S
crystal oscillator,
which is identified automatically.
Crystal oscillator input. Connects the master clock 256 F
S
or 384 F
S
crystal oscillator,
which is identified automatically. External clock pulse is input at this pin.
Digital GND for master clock
Analog GND for Channel 2 output.
Analog positive phase output for Channel 2.
SYMBOL
4-3
HI2559, CXD2559
Absolute Maximum Ratings
T
A
= 25
o
C, V
SS
= 0V
Operating Conditions
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Operating Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . 20
o
C to 75
o
C
Sampling Frequency (F
S
) . . . . . . . . . . . . . . . . . . . . . 7kHz to 50kHz
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . V
SS
-0.5V to 7.0V
Input Voltage (V
1
) . . . . . . . . . . . . . . . . . . . . V
SS
-0.5V to V
DD
+0.5V
Output Voltage (V
0
) . . . . . . . . . . . . . . . . . . V
SS
- 0.5V to V
DD
+0.5V
Operating Temperature (TOPR) . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
Storage Temperature (T
STG
) . . . . . . . . . . . . . . . . . . -55
o
C to 150
o
C
Input/Output Capacitance
Input Pin (C
IN
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9pF (Max.)
Output Pin (C
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11pF (Max.)
Measurement conditions: V
DD
= V
I
= 0V, f = 1MHz
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
APPLICABLE
PIN
DC Electrical Specifications
Input Voltage
V
IH
V
IL
V
IH
V
IL
Output Voltage
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
Input Leakage Current 1
Input Leakage Current 2
Input Leakage Current 3
Input Leakage Current 4
Feedback Resistance
NOTES:
1. Input pins except for *2t
2. ATT, SHIFT, LATCH
3. XCLK
4. XLO
5. AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-)
6. ATT, SHIFT, LATCH, LRCK, BCK, SINt
7. WO
8. CLR, MLSLt
9. MASL
10. XTLI
AC Electrical Specifications
PARAMETER
Oscillation Frequency
256 F
S
384 F
S
External Clock Pulse Input
High Level Width
258 F
S
384 F
S
t
CWH
V
DD
= 5.0
±10%,
TOPR = -20
o
C to 75
o
C
SYMBOL
fx
2
2
38
25
-
-
-
-
13
20
250
250
ns
ns
MHz
I
IL1
I
IL2
I
IL
I
IH
R
FB
I
OH
= -2mA
I
OL
= 4mA
I
OH
= -1mA
I
OL
= 1mA
I
OH
= -4mA
I
OL
= 4mA
V
IN
= V
SS
or V
DD
V
IN
= V
SS
or V
DD
V
IL
= V
SS
V
IH
= V
DD
V
IN
= V
SS
or V
DD
V
DD
-0.8
-
V
DD
/2
-
V
DD
-0.8
0
-10
-40
-40
40
250k
-
-
-
-
-
-
-
-
-100
100
1M
0.4
0.4
-
V
DD
/2
-
-
10
40
-240
240
2.5M
µA
µA
µA
µA
Ω
Note 6
Note 7
Note 8
Note 9
Note 12
V
Note 5
V
Note 4
V
Note 3
0.7 V
DD
-
2.2
-
-
-
-
0.3 V
DD
-
V
Note 2
V
Note 1
4-5
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