IS25CD512/010 & IS25LD020
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory
With 100 MHz Dual-Output SPI Bus Interface
Output SPI Bus Interface
FEATURES
• Low Power Consumption
Memory With 100 MHz Dual-
• Single Power Supply
Interface
Operation
- Typical 10
Memory
read current
MHz Dual-
mA active
With 100
Output SPI Bus
- Low voltage range: 2.70 V – 3.60 V (512Kbit / 1Mbit)
- Typical 15 mA program/erase current
Output SPI Bus Interface
2.30 V – 3.60 V (2Mbit)
• Memory Organization
-
IS25CD512: 64K x 8 (512 Kbit)
- IS25CD010: 128K x 8 (1 Mbit)
- IS25LD020: 256K x 8 (2 Mbit)
• Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4KByte sectors / Two uniform 32KByte
blocks
- 1Mb : Uniform 4KByte sectors / Four uniform 32KByte
blocks
- 2Mb : Uniform 4KByte sectors / Four uniform 64KByte
blocks
• Low standby current 1uA (Typ)
• Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
•
Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
• Sector, Block or Chip Erase Operation
- Maximum 10 ms sector, block or chip erase
• Hardware Write Protection
- Protect and unprotect the device from write operation by
Write Protect (WP#) Pin
• Software Write Protection
-
The Block Protect (BP2, BP1, BP0) bits allow partial or
entire memory to be configured as read-only
• High Product Endurance
- Guaranteed 200,000 program/erase cycles per single
sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin SOIC 150mil
- 8-pin VVSOP 150mil (2Mb)
- 8-pin USON (2x3 mm) (512Kb)
- 8-pin WSON (5x6 mm)
- 8-pin TSSOP
- KGD (Call Factory)
- Lead-free (Pb-free) package
- Automotive Temperature Ranges Available
• Security function
- Built in Safe Guard function and sector unlock function
to make the flash Robust (Appendix1&2)
GENERAL DESCRIPTION
The IS25CD512/010 and IS25LD020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing
single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast
read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging to
perform read, erase and program operations. The devices can be programmed in standard EPROM programmers.
The IS25CD512/010 and IS25LD020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output
(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command
codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program
operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(IS25LD020 is uniform 4
KByte sectors or uniform 64 KByte).
The IS25CD512/010 and IS25LD020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in a variety of packages for all critical needs. The devices operate at wide temperatures between -40°C to +105°C.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
08/12/2013
1
IS25CD512/010 & IS25LD020
CONNECTION DIAGRAMS
CE#
SO
1
8
7
Vcc
HOLD#
CE#
SO
1
2
8 Vcc
7 HOLD#
6 SCK
5 SIO
2
WP# 3
WP#
3
6
SCK
GND 4
GND
4
5
SIO
8-pin WSON
8-Pin SOIC/VVSOP
CE#
SO
WP#
GND
1
2
3
4
8
7
6
5
8-Pin TSSOP
Vcc
HOLD#
SCK
SIO
CE#
SO
WP#
GND
8-Pin USON
Vcc
HOLD#
SCK
SIO
PIN DESCRIPTIONS
SYMBOL
CE#
TYPE
INPUT
DESCRIPTION
SCK
SIO
SO
GND
Vcc
WP#
INPUT
INPUT/OUTPUT
OUTPUT
INPUT
HOLD#
INPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (SlO), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
Serial Data Input/Output
Serial Data Output
Ground
Device Power Supply
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends on the
setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the devices
are not write-protected.
Hold: Pause serial communication by the master device without resetting
the serial sequence.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
08/12/2013
2
IS25CD512/010 & IS25LD020
SPI MODES DESCRIPTION
Multiple IS25CD512/010 and IS25LD020 devices can be
connected on the SPI serial bus and controlled by a SPI
Master, i.e. microcontroller, as shown in Figure 1. The
devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity
when the SPI master is in Stand-by mode: the serial clock
remains at “0” (SCK = 0) for Mode 0 and the clock remains at
“1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both
modes, the input data is latched on the rising edge of Serial
Clock (SCK), and the output data is available from the falling
edge of SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDIO
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
SPI Master
(i.e. Microcontroller)
CS3
CS2
CS1
CE#
SO
SIO
SCK
SO
SIO
SCK
SO
SIO
SPI Memory
Device
SPI Memory
Device
SPI Memory
Devic
e
CE#
WP#
HOLD#
WP#
HOLD#
CE#
WP#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
appropriate.
Figure 2. SPI Modes Supported
SCK
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SIO
Input mode
SO
MSb
MSb
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
08/12/2013
4
嵌入式系统
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