Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> LFE5U-25F-6BG381C

LFE5U-25F-6BG381C: 产品描述USB Interface IC USB to Full Serial UART IC SSOP-20; 产品类别可编程逻辑器件可编程逻辑; 文件大小2MB，共109页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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供应商	器件名称	价格	最低购买	库存
	LFE5U-25F-6BG381C	-	-	点击查看	点击购买

LFE5U-25F-6BG381C概述

USB Interface IC USB to Full Serial UART IC SSOP-20

LFE5U-25F-6BG381C规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Lattice(莱迪斯)
包装说明	,
Reach Compliance Code	compliant
ECCN代码	EAR99
峰值回流温度（摄氏度）	NOT SPECIFIED
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
处于峰值回流温度下的最长时间	NOT SPECIFIED

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ECP5™ and ECP5-5G™ Family

Data Sheet

FPGA-DS-02012 Version 1.8

November 2017

ECP5™ and ECP5-5G™ Family

Data Sheet

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FPGA-DS-02012-1.8

ECP5™ and ECP5-5G™ Family

Data Sheet

Contents

Acronyms in This Document ................................................................................................................................................. 9

1. General Description .................................................................................................................................................... 10

1.1

Features ............................................................................................................................................................ 10

2. Architecture ................................................................................................................................................................ 12

2.1.

Overview ........................................................................................................................................................... 12

2.2

PFU Blocks ......................................................................................................................................................... 13

2.2.1 Slice ............................................................................................................................................................... 14

2.2.2. Modes of Operation...................................................................................................................................... 17

2.3.

Routing .............................................................................................................................................................. 18

2.4.

Clocking Structure ............................................................................................................................................. 18

2.4.1. sysCLOCK PLL ................................................................................................................................................ 18

2.5.

Clock Distribution Network ............................................................................................................................... 19

2.5.1. Primary Clocks .............................................................................................................................................. 20

2.5.2. Edge Clock ..................................................................................................................................................... 21

2.6.

Clock Dividers .................................................................................................................................................... 22

2.7.

DDRDLL .............................................................................................................................................................. 23

2.8.

sysMEM Memory .............................................................................................................................................. 24

2.8.1. sysMEM Memory Block ................................................................................................................................ 24

2.8.2. Bus Size Matching ......................................................................................................................................... 25

2.8.3. RAM Initialization and ROM Operation ........................................................................................................ 25

2.8.4. Memory Cascading ....................................................................................................................................... 25

2.8.5. Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 25

2.8.6. Memory Core Reset ...................................................................................................................................... 26

2.9.

sysDSP™ Slice .................................................................................................................................................... 26

2.9.1. sysDSP Slice Approach Compared to General DSP ....................................................................................... 26

2.9.2. sysDSP Slice Architecture Features ............................................................................................................... 27

2.10. Programmable I/O Cells .................................................................................................................................... 30

2.11. PIO ..................................................................................................................................................................... 32

2.11.1.

Input Register Block .................................................................................................................................. 32

2.11.2.

Output Register Block ............................................................................................................................... 33

2.12. Tristate Register Block ....................................................................................................................................... 34

2.13. DDR Memory Support ....................................................................................................................................... 35

2.13.1.

DQS Grouping for DDR Memory ............................................................................................................... 35

2.13.2.

DLL Calibrated DQS Delay and Control Block (DQSBUF)........................................................................... 36

2.14. sysI/O Buffer ..................................................................................................................................................... 38

2.14.1.

sysI/O Buffer Banks .................................................................................................................................. 38

2.14.2.

Typical sysI/O I/O Behavior during Power-up .......................................................................................... 39

2.14.3.

Supported sysI/O Standards ..................................................................................................................... 39

2.14.4.

On-Chip Programmable Termination ....................................................................................................... 40

2.14.5.

Hot Socketing ........................................................................................................................................... 40

2.15. SERDES and Physical Coding Sublayer ............................................................................................................... 41

2.15.1.

SERDES Block ............................................................................................................................................ 43

2.15.2.

PCS ............................................................................................................................................................ 43

2.15.3.

SERDES Client Interface Bus ..................................................................................................................... 44

2.16. Flexible Dual SERDES Architecture .................................................................................................................... 44

2.17. IEEE 1149.1-Compliant Boundary Scan Testability ........................................................................................... 44

2.18. Device Configuration ......................................................................................................................................... 45

2.18.1.

Enhanced Configuration Options ............................................................................................................. 45

2.18.2.

Single Event Upset (SEU) Support ............................................................................................................ 45

2.18.3.

On-Chip Oscillator .................................................................................................................................... 46

2.19. Density Shifting ................................................................................................................................................. 46

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All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02012-1.8

ECP5™ and ECP5-5G™ Family

Data Sheet

DC and Switching Characteristics................................................................................................................................47

3.1.

Absolute Maximum Ratings ..............................................................................................................................47

3.2.

Recommended Operating Conditions ...............................................................................................................47

3.3.

Power Supply Ramp Rates .................................................................................................................................48

3.4.

Power-On-Reset Voltage Levels ........................................................................................................................48

3.5.

Power up Sequence ...........................................................................................................................................48

3.6.

Hot Socketing Specifications .............................................................................................................................48

3.7.

Hot Socketing Requirements .............................................................................................................................49

3.8.

ESD Performance ...............................................................................................................................................49

3.9.

DC Electrical Characteristics ..............................................................................................................................49

3.10. Supply Current (Standby) ..................................................................................................................................50

3.11. SERDES Power Supply Requirements

1,2,3

...........................................................................................................51

3.12. sysI/O Recommended Operating Conditions ....................................................................................................53

3.13. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................54

3.14. sysI/O Differential Electrical Characteristics .....................................................................................................55

3.14.1.

LVDS ..........................................................................................................................................................55

3.14.2.

SSTLD ........................................................................................................................................................55

3.14.3.

LVCMOS33D..............................................................................................................................................55

3.14.4.

LVDS25E ....................................................................................................................................................56

3.14.5.

BLVDS25....................................................................................................................................................57

3.14.6.

LVPECL33 ..................................................................................................................................................58

3.14.7.

MLVDS25 ..................................................................................................................................................59

3.14.8.

SLVS ..........................................................................................................................................................60

3.15. Typical Building Block Function Performance ...................................................................................................61

3.16. Derating Timing Tables ......................................................................................................................................62

3.17. Maximum I/O Buffer Speed ..............................................................................................................................63

3.18. External Switching Characteristics ....................................................................................................................64

3.19. sysCLOCK PLL Timing .........................................................................................................................................71

3.20. SERDES High-Speed Data Transmitter ...............................................................................................................72

3.21. SERDES/PCS Block Latency ................................................................................................................................73

3.22. SERDES High-Speed Data Receiver ....................................................................................................................74

3.23. Input Data Jitter Tolerance ................................................................................................................................74

3.24. SERDES External Reference Clock......................................................................................................................75

3.25. PCI Express Electrical and Timing Characteristics..............................................................................................76

3.25.1.

PCIe (2.5 Gb/s) AC and DC Characteristics ................................................................................................76

3.25.2.

PCIe (5 Gb/s) – Preliminary AC and DC Characteristics ............................................................................77

3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary....................................................................79

3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics ..................................................................................80

3.27.1.

AC and DC Characteristics ........................................................................................................................80

3.28. CPRI LV E.24 Electrical and Timing Characteristics ............................................................................................80

3.28.1.

AC and DC Characteristics ........................................................................................................................80

3.29. Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics ....................................................81

3.29.1.

AC and DC Characteristics ........................................................................................................................81

3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ...............................82

3.30.1.

AC and DC Characteristics ........................................................................................................................82

3.31. sysCONFIG Port Timing Specifications ..............................................................................................................83

3.32. JTAG Port Timing Specifications ........................................................................................................................88

3.33. Switching Test Conditions .................................................................................................................................89

4. Pinout Information .....................................................................................................................................................91

4.1.

Signal Descriptions ............................................................................................................................................91

4.2.

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................94

4.3.

Pin Information Summary .................................................................................................................................95

4.3.1. LFE5UM/LFE5UM5G .....................................................................................................................................95

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02012-1.8

LFE5U-25F-6BG381C相似产品对比

	LFE5U-25F-6BG381C	LFE5U-25F-6BG381I
描述	USB Interface IC USB to Full Serial UART IC SSOP-20	RS-232 Interface IC 1uA 3-5.5V Tcvr w/AutoShutdown

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