MK2049-02/03
Communications Clock PLLs
Description
The MK2049-02 and MK2049-03 are Phase-
Locked Loop (PLL) based clock synthesizers that
accept multiple input frequencies. With an 8 kHz
clock input as a reference, the MK2049-02/03
generate T1, E1, T3, E3, ISDN, xDSL, and other
communications frequencies. This allows for the
generation of clocks frequency-locked and phase-
locked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems.
The MK2049-02/03 can also accept a T1, E1, T3,
or E3 input clock and provide the same output for
loop timing. All outputs are frequency-locked
together and to the input.
These parts also have a jitter-attenuated buffer
capability. In this mode, the MK2049-02/03 are
ideal for filtering jitter from 27 MHz video clocks
or other clocks with high jitter.
ICS/MicroClock can customize these devices for
many other different frequencies. Contact your
ICS/MicroClock representative for more details.
Features
• Packaged in 20 pin SOIC
• Fixed input-output phase relationship on most
clock selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accept multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-28 MHz
• Lock to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10–28 MHz input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and OC3 submultiples
• 5 V ±5% operation. Refer to MK2049-34 for 3.3 V
Block Diagram
VDD
4
GND
3
RESET
FS3:0
4
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CAP1
CLK1
Clock
Input
Reference
X1
Crystal
Crystal
Oscillator
X2
External/
Loop Timing
Mux
CLK2
CAP2
CLK3
8 kHz
(External
Mode only)
1
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-02/03 B
MK2049-02/03
Communications Clock PLLs
Pin Assignment
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
CLK3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RESET
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20 pin (300 mil) SOIC
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
CLK3
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RESET
FS0
Type
I
XO
XI
P
P
P
P
O
O
O
I
I
I
P
P
LF
P
LF
I
I
Description
Frequency Select 1. Determines CLK input/outputs per tables on pages 4 & 5.
Crystal connection. Connect to a MHz crystal as shown in the tables on pages 4 & 5.
Crystal connection. Connect to a MHz crystal as shown in the tables on pages 4 & 5.
Connect to +5V.
Connect to +5V.
Connect to +5V.
Connect to ground.
Clock 2 output determined by status of FS3:0 per tables on pages 4 & 5.
Clock 1 output determined by status of FS3:0 per tables on pages 4 & 5. Always 1/2 of CLK2.
Clock 3 as shown in tables on pages 4 &5; typically recovered 8 kHz clock output.
Frequency Select 2. Determines CLK input/outputs per tables on pages 4 & 5.
Frequency Select 3. Determines CLK input/outputs per tables on pages 4 & 5.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Connect to +5V.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
Reset pin. Resets internal PLL when low. Outputs will stop low. Internal pull-up resistor.
Frequency Select 0. Determines CLK input/outputs per tables on pages 4 & 5.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
2
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-02/03 B
MK2049-02/03
Communications Clock PLLs
Electrical Specifications
Parameter
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance, FS3:0
Input Frequency, External Mode
Input Clock Pulse Width
Propagation Delay
Output-Output Skew, Zero Delay Selections
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Actual mean frequency error versus target
Conditions
Referenced to GND
MK2049-0xS
MK2049-0xSI
Max of 10 seconds
-0.5
0
-40
-65
4.75
2
Pin 19 only
Pin 19 only
IOH=-4 mA
IOH=-8 mA
IOL=8 mA
No Load, VDD=5.0V
Each output
VDD-0.5
0.5
VDD-0.4
2.4
0.4
20
±100
7
8.000
10
ICLK to CLK2
CLK1 to CLK2, Note 2
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
Any clock selection
0
2
500
1.5
1.5
60
0
5
Minimum
Typical
Maximum
7
VDD+0.5
70
85
250
150
5.25
0.8
Units
V
V
°C
°C
°C
°C
V
V
V
V
V
V
V
V
mA
mA
pF
kHz
ns
ns
ps
ns
ns
%
ppm
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC CHARACTERISTICS (VDD = 5V unless noted)
AC CHARACTERISTICS (VDD = 5V unless noted)
ICLK
40
0
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CLK1 in the MK2049-02 may have the rising or falling edge aligned with the rising edge of CLK2. See the INPUT AND
OUTPUT SYNCHRONIZATION section for more details.
3
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-02/03 B
MK2049-02/03
Communications Clock PLLs
MK2049-02 Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
CLK1
(Note 3)
1.544
2.048
22.368
17.184
19.44
16.384
24.576
25.92
10.24
4.096
CLK2
3.088
4.096
44.736
34.368
38.88
32.768
49.152
51.84
20.48
8.192
Crystal
12.352
12.288
11.184
11.456
12.96
8.192
12.288
12.96
10.24
12.288
CLK3
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
MK2049-02 Output Decoding Table – Loop Timing Mode (MHz)
ICLK
1.544
2.048
44.736
34.368
FS3 FS2 FS1 FS0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
CLK1
(Note 3)
1.544
2.048
22.368
17.184
CLK2
3.088
4.096
44.736
34.368
Crystal
12.352
12.288
11.184
11.456
CLK3
N/A
N/A
N/A
N/A
MK2049-02 Output Decoding Table – Buffer Mode (MHz)
ICLK
19 - 28
10 - 14
FS3 FS2 FS1 FS0
1
1
1
1
1
1
0
1
CLK1
(Note 3)
ICLK/2
2*ICLK
CLK2
ICLK
4*ICLK
Crystal
ICLK/2
ICLK
CLK3
N/A
N/A
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
= No Zero (Fixed) I/O Delay for these selections shown in the shaded boxes.
Note 3: CLK1 rising or falling edge may align with the input clock. See Figure 1 on page 6
for more details.
4
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-02/03 B
MK2049-02/03
Communications Clock PLLs
MK2049-03 Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
CLK1
1.544
2.048
18.688
7.68
19.44
16.384
24.576
8.64
12.416
18.528
10.24
4.096
CLK2
3.088
4.096
37.376
15.36
38.88
32.768
49.152
17.28
24.832
37.056
20.48
8.192
CLK3
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
1.544 MHz
8 kHz
8 kHz
Crystal
12.352
12.288
9.344
10.24
9.72
8.192
12.288
11.52
12.416
12.352
10.24
8.192
= No Zero (Fixed) I/O Delay for these selections shown in the shaded boxes.
MK2049-03 Output Decoding Table – Loop Timing Mode (MHz) for T1/E1
ICLK
1.544
2.048
FS3 FS2 FS1 FS0
1
0
0
0
1
0
0
1
CLK1
1.544
2.048
CLK2
3.088
4.096
Crystal
12.352
12.288
CLK3
N/A
N/A
MK2049-03 Output Decoding Table – Buffer Mode (MHz)
ICLK
19 - 28
10 - 14
FS3 FS2 FS1 FS0
1
1
1
0
1
1
1
1
CLK1
ICLK/2
2*ICLK
CLK2
ICLK
4*ICLK
Crystal
ICLK/2
ICLK
CLK3
N/A
Low
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
OPERATING MODES
The MK2049-02/03 have three operating modes: External, Loop Timing, and Buffer. Although each
mode uses an input clock to generate various output clocks, there are important differences in their input
and crystal requirements.
External Mode
The MK2049-02/03 accept an external 8 kHz clock and will produce a number of common communica-
tion clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on”
pulse as narrow as 10 ns is acceptable. In the MK2049-02, the rising edge of CLK2 is aligned with the
rising edge of the 8 kHz ICLK; refer to Figure 1 for more details. In the MK2049-03, the rising edges of
CLK1 and CLK2 are both aligned with the rising edge of the 8 kHz ICLK (unless noted in the shaded area
of the table); refer to Figure 2 for more details.
5
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-02/03 B
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
