PTN5100D
USB Type-C power delivery PHY and protocol IC
Rev. 1 — 2 August 2016
Product data sheet
1. General description
PTN5100D is a single port USB Type-C Power Delivery (PD) PHY and Protocol IC that
provides Type-C Configuration channel interface and USB PD Physical and Protocol layer
functions to a System PD Port Policy Controller (Policy Engine and Device Policy
Manager, Alternate mode controller). It complies with USB PD[1] and Type-C[2]
specifications. PTN5100D is architected to deliver robust performance, compliant
behavior, configurability and system implementation flexibility that are essential to tide
over interoperability and compliance hurdles in the platform applications.
PTN5100D can support system realization of the following PD roles: (i) Consumer only
(ii) Consumer/Provider. Further, it is register programmed to operate in Type-C specific
Upstream Facing Port (UFP). It can work along with the PD policy controller to operate in
other modes (DFP, DRP).
PTN5100D operates from platform power supply VDD, or it can also be powered from
USB power VBUS directly. The host interface operates on VIO supply to facilitate
interfacing to systems that use IO supply rail different from VDD supply rail.
It provides SPI/I2C interface for system host control/status update. The interface choice is
pre-configured in NXP factory.
PTN5100D is available in a small footprint package option: HVQFN20 4 mm x 4 mm,
0.5 mm pitch.
2. Features and benefits
2.1 USB PD and Type-C Features
Complies with USB PD[1] and USB Type-C[2] specifications.
Supports implementation of various system PD roles: Consumer, Consumer/Provider
Supports Type-C role configurability
Type-C role (UFP, DFP)
Implements UFP role pull down behavior to handle dead battery condition on
battery powered platforms
Implements 'Rd' indication on CC pin
Cooperatively works under the control of Policy controller MCU for power delivery
negotiation and contract(s), Alternate mode and VDM exchanges
Implements BMC (de)coding, 4B5B symbol (de)coding, CRC generation/checking,
PD packet assembling/disassembling including Preamble, SOP, EOP, Good CRC
response, Retries, Hard and Cable resets
PD PHY and Protocol layer interface control and status update handled via SPI/I2C
interface
NXP Semiconductors
PTN5100D
USB Type-C power delivery PHY and protocol IC
DRP and DFP roles can be supported
2.2 System protection features
Back current protection on all pins when PTN5100D is unpowered
CC1 and CC2 pins are 5.5 V tolerant
VBUS pin and VBUS power path MOSFET enable pins are 28 V tolerant
2.3 General
Delivers (active LOW enable) gate control signals for PMOS Power MOSFETs on
VBUS source and sink power paths
Provides dedicated IO pin (CC_ORIENT) for indicating Cable/plug orientation
Delivers up to 30 mA (max) for powering Policy controller MCU
Supports SPI slave interface (SPI modes 1 and 2 supported) up to 30 MHz
Supports I2C slave interface standard mode (100 kHz), Fast mode (400 kHz) and Fast
mode plus (1 MHz)
I2C Device slave address programmable up to 3 values
Supports 3.3 V or 1.8 V capable I
2
C-bus or SPI interface
Supports register access - device configuration, control and status/interrupt
interfacing through Slave I
2
C-bus interface
Power supplies - VDD (3.3 V
10
%) or VBUS
Tolerant up to 28 V on VBUS and operational up to maximum of 25 V on VBUS
Operating temperature
20 C
to 85
C
ESD 8 kV HBM, 1 kV CDM
Package: HVQFN20 4 mm
4 mm, 0.5 mm pitch.
3. Applications
PC accessories/peripherals: Docking, Mobile Monitors, Multi-Function Monitors,
Portable/External hard drives, Dongles and accessories, etc.
4. Ordering information
Table 1.
Ordering information
Topside
marking
51D0
51DA
Package
Name
HVQFN20
HVQFN20
Description
plastic thermal enhanced very thin quad flat package;
no leads; 20 terminals; body 4
4
0.85 mm
[2]
plastic thermal enhanced very thin quad flat package;
no leads; 20 terminals; body 4
4
0.85 mm
[3]
Version
SOT917-4
SOT917-4
Type number
PTN5100DBS
PTN5100DABS
[1]
[2]
[3]
Total height after printed-circuit board mounting <=1 mm (maximum)
Supported system interface - SPI
Supported system interface - I
2
C
PTN5100D
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2016
2 of 37
NXP Semiconductors
PTN5100D
USB Type-C power delivery PHY and protocol IC
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PTN5100DBSMP
Package
HVQFN20
Packing method
Minimum
order quantity
Temperature
T
amb
=
20 C
to +85
C
Type number
PTN5100DBS
Reel 13" Q2/T3
6000
*standard mark SMD
dry pack
Reel 13" Q2/T3
6000
*standard mark SMD
dry pack
PTN5100DABS
PTN5100DABSMP
HVQFN20
T
amb
=
20 C
to +85
C
5. Block diagram
EN_USBFET1
EN_USBFET2
EN_USBSRC
BYPASS
VBUS
VDD
FET CONTROL
AND STATUS
TST0/TST1
VBUS
LDO
USB PD PHY
USB PD
PROTOCOL
GND
VIO
V_MCUPWR
INTERNAL LDO AND
POWER DISTRIBUTION
SLV_ADDR
INT_N
CC1
CC2
CC_ORIENT
CC_CTRL1
CC BLOCK
NVM
REGISTER
INTERFACE
I2C SLAVE
INTERFACE
SPI SLAVE
INTERFACE
SPI_CS
SPI_MOSI_I2C_SDA
SPI_MISO
SPI_CLK_I2C_SCL
aaa-018479
Fig 1.
PTN5100D block diagram
PTN5100D
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2016
3 of 37
NXP Semiconductors
PTN5100D
USB Type-C power delivery PHY and protocol IC
6. Pinning information
6.1 Pinning
20
EN_USBFET2
17
V_MCUPWR
terminal 1
index area
EN_USBFET1
VBUS
EN_USBSRC
CC2
CC1
1
2
3
4
5
CC_CTRL1 10
6
7
8
9
16 SPI_MISO
15 VDD
14 SLV_ADDR
13 INT_N
12
SPI_MOSI_I2C_SDA
11
SPI_CLK_I2C_SCL
19 BYPASS
PTN5100D
18 VIO
TST0
CC_ORIENT
SPI_CS
TST1
aaa-018288
Transparent top view
Note: HVQFN20 package ground is connected to exposed center pad. The exposed center pad
must be connected to platform supply ground for proper device operation. For enhanced thermal,
electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the PCB in the thermal pad region.
Fig 2.
Pin configuration for HVQFN20
PTN5100D
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2016
4 of 37
NXP Semiconductors
PTN5100D
USB Type-C power delivery PHY and protocol IC
6.2 Pin description
Table 3.
Symbol
EN_USBSRC
Pin description
Pin
3
Pin
Pin Type
direction
Output
Open drain
Description
USB PD VBUS Source Power path PMOS FET gate
Active Low enable.
At default/POR, this pin is Hi-Z; PTN5100D drives
this pin LOW based on Type-C connection state
and/or policy controller MCU command.
The pin status can be read in the internal register(s).
EN_USBFET1
1
Output
Open drain
USB PD VBUS Source or Sink Power path PMOS
FET gate Active Low enable.
At default/POR, this pin is Hi-Z; PTN5100D drives
this pin LOW based on Type-C connection state
and/or policy controller MCU command.
The pin status can be read in the internal register(s).
EN_USBFET2
20
Output
Open drain
USB PD VBUS Source or Sink Power path PMOS
FET gate Active Low enable.
At default/POR, this pin is Hi-Z; PTN5100D drives
this pin LOW based on policy controller MCU
command.
The pin status can be read in the internal register(s).
CC1
5
IO
Custom IO
Type-C Configuration channel #1
TVS or similar protection diode (e.g.
PESD5V0S1USF, PESD5V0S1UL, etc.) shall be
used to protect the CC1/2 pins from
overshoot/undershoot during cable plug/unplug and
cable discharge events.
CC2
4
IO
Custom IO
Type-C Configuration channel #2
TVS or similar protection diode (e.g.
PESD5V0S1USF, PESD5V0S1UL, etc.) shall be
used to protect the CC1/2 pins from
overshoot/undershoot during cable plug/unplug and
cable discharge events.
CC_ORIENT
9
Output
CMOS IO on VIO power
rail
This pin indicates Type-C cable plug orientation.
The pin's polarity is inverted at power-on reset and
the PD policy controller MCU has to initialize
PTN5100D before the pin level is valid. After the
initialization, the pin indicates orientation as follows:
LOW = Normal plug orientation (CC communication
on CC1)
HIGH = Reverse plug orientation (CC
communication on CC2)
Default pin value is LOW even if there is no
connection or normal plug connection
CC_CTRL1
TST1
10
6
Input
Output
Analog Input
CMOS IO on VIO power
rail
Input to indicate whether to present ‘Rd’ or Open on
CC pin under Unpowered condition
Meant for Test purpose only. Do not connect in the
application
PTN5100D
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2016
5 of 37
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