74LV4094
8-stage shift-and-store bus register
Rev. 4 — 19 December 2011
Product data sheet
1. General description
The 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional compatible
with 74HC4094; 74HCT4094.
The 74LV4094 is an 8-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input to parallel buffered 3-state outputs
QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive-going clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094
devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
74LV4094 devices when the clock has a slow rise time.
2. Features and benefits
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
C
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
NXP Semiconductors
74LV4094
8-stage shift-and-store bus register
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV4094N
74LV4094D
74LV4094DB
74LV4094PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
plastic small outline package; 16 leads; body width 3.9 SOT109-1
mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT338-1
SOT403-1
5. Functional diagram
3
CP
1
STR
QS1
QS2
QP0
QP1
QP2
2
D
QP3
QP4
QP5
QP6
QP7
OE
15
7
14
13
12
11
9
10
4
5
6
3
2
1
15
C2
EN3
SRG8
C1/
1D
2D
3
4
5
6
7
14
13
12
11
9
10
001aaf111
001aaf112
Fig 1.
Functional diagram
Fig 2.
Logic symbol
74LV4094
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2011
2 of 21
NXP Semiconductors
74LV4094
8-stage shift-and-store bus register
2
3
D
CP
8-STAGE SHIFT
REGISTER
QS2
QS1
STR
8-BIT STORAGE
REGISTER
10
9
1
15
OE
3-STATE OUTPUTS
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
4
5
6
7
14
13
12
11
001aaf119
Fig 3.
Logic diagram
STAGE 0
D
D
CP
FF 0
CP
CP
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
CP
FF 7
D
LE
LATCH
Q
QS2
Q
QS1
D
LE
Q
D
LE
Q
LATCH 0
STR
LATCH 7
OE
QP0
QP1
QP2
QP3
QP4
QP5
QP6
QP7
001aag799
Fig 4.
Logic diagram
74LV4094
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2011
3 of 21
NXP Semiconductors
74LV4094
8-stage shift-and-store bus register
6. Pinning information
6.1 Pinning
74LV4094
STR
D
CP
QP0
QP1
QP2
QP3
GND
1
2
3
4
5
6
7
8
001aaf120
16 V
CC
15 OE
14 QP4
13 QP5
12 QP6
11 QP7
10 QS2
9
QS1
STR
D
CP
QP0
QP1
QP2
QP3
GND
1
2
3
4
5
6
7
8
001aan680
74LV4094
16 V
CC
15 OE
14 QP4
13 QP5
12 QP6
11 QP7
10 QS2
9
QS1
Fig 5.
Pin configuration DIP16 and SO16
Fig 6.
Pin configuration SSOP16 and TSSOP16
6.2 Pin description
Table 2.
Symbol
STR
D
CP
QP0 to QP7
V
SS
QS1, QS2
OE
V
DD
Pin description
Pin
1
2
3
4, 5, 6, 7, 14, 13, 12, 11
8
9,10
15
16
Description
strobe input
data input
clock input
parallel output
ground supply voltage
serial output
output enable input
supply voltage
74LV4094
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2011
4 of 21
NXP Semiconductors
74LV4094
8-stage shift-and-store bus register
7. Functional description
Table 3.
Inputs
CP
[1]
Function table
[1]
Parallel outputs
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
QP0
Z
Z
NC
L
H
NC
QPn
Z
Z
NC
QPn
1
QPn
1
NC
Serial outputs
QS1
Q6S
NC
Q6S
Q6S
Q6S
NC
QS2
NC
Q7S
NC
NC
NC
Q7S
At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition;
= negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
Z-state
Z-state
Fig 7.
Timing diagram
74LV4094
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 19 December 2011
5 of 21
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