DATASHEET
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-33
Description
The ICS1894-33 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and
100Base-TX Carrier-Sense Multiple Access/Collision
Detection (CSMA/CD) Ethernet standards, ISO/IEC
8802.3. It is intended for RMII Node applications and
includes the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
The ICS1894-33 incorporates Digital-Signal Processing
(DSP) control in its Physical-Medium Dependent (PMD)
sub-layer. As a result, it can transmit and receive data on
unshielded twisted-pair (UTP) category 5 cables with
attenuation in excess of 24 dB at 100MHz.
The ICS1894-33 provides a Serial-Management Interface
for exchanging command and status information with a
Station-Management (STA) entity. The ICS1894-33
Media-Dependent Interface (MDI) can be configured to
provide half/full-duplex operation at data rates of 10 Mb/s or
100Mb/s.
In addition, the ICS1894-33 includes a programmable LED
and interrupt output function. The LED outputs can be
configured through registers to indicate the occurance of
certain events such as LINK, ACTIVITY, etc. The purpose
of the programmable interrupt output is to notify the PHY
controller device immediately when a certain event
happens instead of having the PHY controller continuously
poll the PHY. The events that could be used to generate
interrupts are: receiver error, Jabber, page received,
parallel detect fault, link partner acknowledge, link status
change, auto-negotiation complete, remote fault, etc.
The ICS1894-33 has deep power modes that can result in
significant power savings when the link is broken.
Applications:
NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
•
Supports category 5 cables and above with attenuation in
excess of 24dB at 100 MHz.
•
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
•
10Base-T and 100Base-TX ISO/IEC 8802.3 compliant
•
MIIM (MDC/MDIO) management bus for PHY register
configuration
•
RMII interface support with external 50 MHz system clock
•
Single 3.3V power supply
•
Highly configurable, supports:
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M half/full duplex modes
•
•
•
•
•
•
Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 300 mW)
Power-Down mode (typically 21mW)
Programmable LEDs
Interrupt output pin
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
•
•
•
•
•
Core power supply (3.3 V)
3.3 V/1.8 V VDDIO operation supported
Smart power control with deep power down feature
Available in 32-pin (5mm x 5mm) QFN package, Pb-free
Available in Industrial Temp and Lead Free
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Block Diagram
100Base-T
10/100 RMII
MAC
Interface
Interface
MUX
PCS
• Framer
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Smart Power
Control
Block
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
Pin Assignment
P1/ISO/LED1
P0/LED0
REFIN
NC
VSS
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
1
25
VDDD
TXD1
VSS
TXD0
TXEN
SPEED
NLG32 With Ground
Connecting to Thermal Pad
NOD/RXER
ANSEL
VDDIO
RMII/RXDV
9
17
FDPX/RXD0
P2/INT
MDIO
MDC
VSS
AMDIX
RESET_N
P3
32-pin 5mm x 5mm QFN
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
RXTR1RXD1
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin
Name
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
MDIO
MDC
AMDIX
P3
RXTRI/
RXD1
FDPX/
RXD0
RMII/RXDV
VDDIO
ANSEL
NOD/
RXER
SPEED
TXEN
TXD0
VDDD
TXD1
VSS
VSS
NC
REFIN
Pin
Type
1
AIO
AIO
Power
AIO
AIO
Power
AIO
Pin Description
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via resistors (see
“Recommended Component Values” table and the “ICS1894-33 TCSR” figure).
Hardware reset for the entire chip (active low)
PHY address Bit 2 as input (during power on reset/hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
AMDIX enable as input (during power on reset/hardware reset)
PHY address Bit 3 as input (during power on reset/hardware reset)
RX tri-state enable as input (during power on reset/hardware reset)
Receive data Bit 1 in RMII mode as output.
Half/Full duplex enable as input (during power on reset/hardware reset)
Receive data Bit 0 in RMII mode as output
RMII select as input (during power on reset/hardware reset). Connect this pin to
VDDIO using a 1k resistor. CRS_DV in RMII mode as output.
3.3 V/1.8 V IO Power Supply.
Auto-negotiation enable as input (during power on reset/hardware reset)
Node select as input (during power on reset/hardware reset)
Receive error in RMII mode as output
It is recommended to always pull this pin low on power-up or hardware reset.
10M/100M select as input (during power on reset/hardware reset)
Transmit enable in RMII mode
Transmit data Bit 0 in RMII mode
3.3 V Power Supply
Transmit data Bit 1 in RMII mode
Ground Connect to ground.
Ground Connect to ground.
Input
IO/Ipd
IO
Input
IO/Ipu
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
Power
IO/Ipu
IO/Ipd
22
23
24
25
26
27
28
29
30
IO/Ipu
Input
Input
Power
Input
Ground Connect this pin to GND
Ground Connect this pin to GND
—
Input
No connect.
50 MHz clock input in RMII mode.
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
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PHYCEIVER
Pin
Number
31
32
Pin
Name
P0/LED0
P1/ISO/LED1
Pin
Type
1
IO
IO
Pin Description
PHY address Bit 0 as input (during power on reset/hardware reset) and LED # 0
(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset/hardware reset) and LED # 1
(function configurable, default is "10/100 mode") as output; After latch, alternates as
a real time receiver isolation input.
PADDLE
Notes:
VSS
Ground Connect to ground.
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
3. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
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10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
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PHYCEIVER
Strapping Options
Pin
Number
14
15
11
31
32
16
17
Pin
Name
AMDIX
P3
P2/INT
P0/LED0
P1/ISO/LED1
RXTRI/RXD1
FDPX/RXD0
Pin
Type
1
IO/Ipu
IO/Ipd
IO/Ipd
IO
IO
IO/Ipd
IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
Pin Function
The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
1 = Real time receiver isolation function enable
3
; 0 = Receiver Tristate Disable
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
1 = RMII mode
0 = Not supported
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode (mode not supported)
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
18
20
21
22
RMII/RXDV
ANSEL
NOD/RXER
SPEED
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
1.
IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2.
IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
IDT®
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