CBTL06DP213
Third generation high-performance DisplayPort multiplexer
Rev. 4 — 23 March 2017
Product data sheet
1. General description
CBTL06DP213 is an NXP third generation high-performance multi-channel multiplexer,
meant for DisplayPort (DP) v1.3 or Embedded DisplayPort applications operating at data
rate of 1.62 Gbit/s, 2.7 Gbit/s, 5.4 Gbit/s or 8.1 Gbit/s. It is designed using NXP proprietary
high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1
multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable
of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and
Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated
AUX and DDC I/Os, CBTL06DP213 provides an additional level of multiplexing of AUX
and DDC signals delivering true flexibility and choice.
A typical application of CBTL06DP213 is on motherboards where one of two GPU
DisplayPort sources needs to be selected to connect to a DisplayPort sink device or
connector. A controller chip selects which path to use by setting a select signal HIGH or
LOW. Due to the bidirectional nature of the signal paths, CBTL06DP213 can also be used
in the reverse topology, for example, to connect one display source device to one of two
display sink devices or connectors.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.3 - 8.1 Gbit/s) signals
4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
main link signals
1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
1 channel with 2 : 1 multiplexing/switching for HPD signal
High-bandwidth analog pass-gate technology
R
on
on DP high-speed channels: 14
Low insertion loss:
0.9
dB at 100 MHz
1.3
dB at 2.7 GHz
1.7
dB at 4 GHz
3
dB at 11.1 GHz
Low crosstalk:
35
dB at 2.7 GHz
Low off-state isolation:
30
dB at 2.7 GHz,
25
dB at 4 GHz
Low return loss:
20.3
dB at 100 MHz
16.7
dB at 1.35 GHz
12.9
dB at 2.7 GHz
12
dB at 4 GHz
NXP Semiconductors
CBTL06DP213
Third generation high-performance DisplayPort multiplexer
Very low intra-pair skew (5 ps typical)
Very low inter-pair skew (< 80 ps)
Switch/multiplexer position select CMOS input
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor
Supports HDMI/DVI incorrect dongle connection
Single 3.3 V power supply
Operation current of 2 mA typical,
ESD 2 kV HBM, 500 V CDM
Available in 5 mm
5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
Motherboard applications requiring DisplayPort and PCI Express
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Topside
mark
6D213
Solder process
Package
Name
Pb-free (SnAgCu TFBGA48
solder compound)
Description
Version
plastic thin fine-pitch ball grid array package; SOT918-1
48 balls; body 5
5
0.8 mm
[1]
Type number
CBTL06DP213EE
[1]
Total height including solder balls after printed circuit board mounting = 1.15 mm maximum.
For more information on product marking, refer to
www.nxp.com/products/related/package-markings.html.
4.1 Ordering options
Table 2.
Ordering options
Orderable part number Package
Packing method
Minimum
order
quantity
3000
Temperature
Type number
CBTL06DP213EE
CBTL06DP213EE,118
TFBGA48
Reel 13” Q1/T1
*standard mark SMD
T
amb
=
40 C
to +105
C
CBTL06DP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 23 March 2017
2 of 17
NXP Semiconductors
CBTL06DP213
Third generation high-performance DisplayPort multiplexer
5. Functional diagram
VDD
CBTL06DP213
4
IN1_n+
IN1_n−
IN2_n+
IN2_n−
0
4
4
OUT_n+
OUT_n−
1
AUX1+
AUX1−
AUX2+
AUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
00
10
AUX+ or SCL
AUX− or SDA
AUX+
AUX−
01
11
HPD_1
0
HPDIN
HPD_2
1
GPU_SEL
DDC_AUX_SEL
TST0
GND
002aag784
Fig 1.
Functional diagram
CBTL06DP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 23 March 2017
3 of 17
NXP Semiconductors
CBTL06DP213
Third generation high-performance DisplayPort multiplexer
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL06DP213EE
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aag785
Transparent top view
Fig 2.
Pin configuration for TFBGA48
1
A
B
C
D
E
F
G
H
J
AUX−
HPDIN
OUT_1−
OUT_2−
OUT_3−
GPU_SEL
OUT_0−
2
VDD
OUT_0+
DDC_AUX
_SEL
OUT_1+
OUT_2+
OUT_3+
GND
AUX+
HPD_1
3
4
IN1_0−
5
IN1_1−
IN1_1+
6
IN1_2−
IN1_2+
7
8
IN1_3+
9
IN1_3−
IN2_0−
GND
IN1_0+
TST0
IN2_0+
GND
IN2_1+
IN2_2+
IN2_3+
GND
IN2_1−
IN2_2−
IN2_3−
HPD_2
GND
VDD
DDC_CLK2
DDC_DAT2
AUX2+
AUX2−
GND
DDC_CLK1
DDC_DAT1
AUX1+
AUX1−
002aag786
Transparent top view
Fig 3.
Ball mapping
CBTL06DP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 23 March 2017
4 of 17
NXP Semiconductors
CBTL06DP213
Third generation high-performance DisplayPort multiplexer
6.2 Pin description
Table 3.
Symbol
GPU_SEL
Pin description
Ball
A1
Type
3.3 V CMOS
single-ended input
Description
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX I/Os are connected to their
respective DDCOUT terminals.
Test pin for NXP use only. Should be tied to V
DD
in the application
use cases.
Four high-speed differential pairs for DisplayPort signals, path 1,
left-side.
DDC_AUX_SEL
C2
3.3 V CMOS
single-ended input
TST0
IN1_0+
IN1_0
IN1_1+
IN1_1
IN1_2+
IN1_2
IN1_3+
IN1_3
IN2_0+
IN2_0
IN2_1+
IN2_1
IN2_2+
IN2_2
IN2_3+
IN2_3
OUT_0+
OUT_0
OUT_1+
OUT_1
OUT_2+
OUT_2
OUT_3+
OUT_3
AUX1+
AUX1
AUX2+
AUX2
DDC_CLK1
DDC_DAT1
B7
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
H6
J6
H8
J8
3.3 V CMOS
single-ended input
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
Four high-speed differential pairs for DisplayPort signals, path 2,
left-side.
Four high-speed differential pairs for DisplayPort signals,
right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
Pair of single-ended terminals for DDC clock and data signals,
path 1, left-side.
CBTL06DP213
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 4 — 23 March 2017
5 of 17
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