PRELIMINARY
Programmable System-on-Chip (PSoC )
General Description
PSoC
®
5LP: CY8C58LP Family
Datasheet
®
With its unique array of configurable blocks, PSoC
®
5LP is a true system-level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C58LP family is also a high-performance configurable digital system with
some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN).
In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and
a high-performance 32-bit ARM
®
Cortex™-M3 microprocessor core. You can easily create system-level designs using a rich library
of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP
family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute
design changes through simple firmware updates.
❐
Library of advanced peripherals
Features
• Cyclic redundancy check (CRC)
■
32-bit ARM Cortex-M3 CPU core
• Pseudo random sequence (PRS) generator
❐
DC to 67 MHz operation
• Local interconnect network (LIN) bus 2.0
❐
Flash program memory, up to 256 KB, 100,000 write cycles,
• Quadrature decoder
20-year retention, and multiple security features
■
Analog peripherals (1.71 V
≤
V
DDA
≤
5.5 V)
❐
Up to 32-KB flash error correcting code (ECC) or configura-
tion storage
❐
1.024 V ±0.1% internal voltage reference across –40°C to
+85°C
❐
Up to 64 KB SRAM
❐
Configurable delta-sigma ADC with 8- to 20-bit resolution
❐
2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 M cycles, and 20 years retention
• Sample rates up to 192 ksps
❐
24-channel direct memory access (DMA) with multilayer
• Programmable gain stage: ×0.25 to ×16
AHB
[1]
bus access
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
• Programmable chained descriptors and priorities
ratio (SINAD), ±1-bit INL/DNL
• High bandwidth 32-bit transfer support
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL
■
Low voltage, ultra low power
❐
Up to two SAR ADCs, each 12-bit at 1 Msps
❐
Wide operating voltage range: 0.5 V to 5.5 V
❐
Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs
❐
High-efficiency boost regulator from 0.5 V input to 1.8 V to
❐
Four comparators with 95-ns response time
5.0 V output
❐
Four uncommitted opamps with 25-mA drive capability
❐
3.1 mA at 6 MHz
❐
Four configurable multifunction analog blocks. Example con-
❐
Low power modes including:
figurations are programmable gain amplifier (PGA), tran-
simpedance amplifier (TIA), mixer, and sample and hold
• 2-µA sleep mode with real time clock (RTC) and low-volt-
age detect (LVD) interrupt
❐
CapSense support
• 300-nA hibernate mode with RAM retention
■
Programming, debug, and trace
■
Versatile I/O system
❐
JTAG (4 wire), serial wire debug (SWD) (2 wire), single wire
[2]
viewer (SWV), and TRACEPORT interfaces
❐
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs )
❐
Cortex-M3 flash patch and breakpoint (FPB) block
❐
Any GPIO to any digital or analog peripheral routability
❐
Cortex-M3 Embedded Trace Macrocell™ (ETM™) gener-
❐
LCD direct drive from any GPIO, up to 46×16 segments
®
support from any GPIO
[3]
ates an instruction trace stream.
❐
CapSense
❐
Cortex-M3 data watchpoint and trace (DWT) generates data
❐
1.2 V to 5.5 V I/O interface voltages, up to 4 domains
trace information
❐
Maskable, independent IRQ on any pin or port
❐
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
❐
Schmitt-trigger transistor-transistor logic (TTL) inputs
used for printf-style debugging
❐
All GPIOs configurable as open drain high/low,
❐
DWT, ETM, and ITM blocks communicate with off-chip debug
pull-up/pull-down, High-Z, or strong output
and trace systems via the SWV or TRACEPORT
2
❐
Configurable GPIO pin state at power-on reset (POR)
❐
Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
❐
25 mA sink on SIO
■
Digital peripherals
❐
20 to 24 programmable
logic device (PLD)
based universal
digital blocks (UDBs)
[2]
❐
Full CAN 2.0b 16 RX, 8 TX buffers
[2]
❐
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
❐
Four 16-bit configurable timers, counters, and PWM blocks
❐
67-MHz, 24-bit fixed point digital filter block (DFB) to
implement finite impulse response (FIR) and infinite impulse
response (IIR) filters
❐
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I
2
C
• Many others available in catalog
■
■
Precision, programmable clocking
❐
3- to 62-MHz internal oscillator over full temperature and volt-
age range
❐
4- to 25-MHz crystal oscillator for crystal PPM accuracy
❐
Internal PLL clock generation up to 67 MHz
❐
32.768-kHz watch crystal oscillator
❐
Low power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
❐
–40 °C to +85 °C degrees industrial temperature
❐
68-pin QFN and 100-pin TQFP package options.
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See
Ordering Information on page 115
for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation
Document Number: 001-84932 Rev. **
•
198 Champion Court
•
San Jose CA 95134-1709
,
•
408-943-2600
Revised December 7, 2012
PRELIMINARY
PSoC
®
5LP: CY8C58LP Family
Datasheet
Contents
1. Architectural Overview ................................................. 3
2. Pinouts ........................................................................... 5
3. Pin Descriptions ............................................................ 9
4. CPU ............................................................................... 11
4.1 ARM Cortex-M3 CPU ...........................................11
4.2 Cache Controller ..................................................12
4.3 DMA and PHUB ...................................................12
4.4 Interrupt Controller ...............................................15
5. Memory ......................................................................... 17
5.1 Static RAM ...........................................................17
5.2 Flash Program Memory ........................................17
5.3 Flash Security .......................................................17
5.4 EEPROM ..............................................................17
5.5 Nonvolatile Latches (NVLs) ..................................18
5.6 External Memory Interface ...................................19
5.7 Memory Map ........................................................20
6. System Integration ...................................................... 21
6.1 Clocking System ...................................................21
6.2 Power System ......................................................24
6.3 Reset ....................................................................28
6.4 I/O System and Routing .......................................29
7. Digital Subsystem ....................................................... 36
7.1 Example Peripherals ............................................36
7.2 Universal Digital Block ..........................................38
7.3 UDB Array Description .........................................41
7.4 DSI Routing Interface Description ........................41
7.5 CAN ......................................................................43
7.6 USB ......................................................................44
7.7 Timers, Counters, and PWMs ..............................44
7.8 I
2
C ........................................................................45
7.9 Digital Filter Block .................................................46
8. Analog Subsystem ...................................................... 46
8.1 Analog Routing .....................................................48
8.2 Delta-sigma ADC ..................................................50
8.3 Successive Approximation ADC ...........................51
8.4 Comparators .........................................................51
8.5 Opamps ................................................................53
8.6 Programmable SC/CT Blocks ..............................53
8.7 LCD Direct Drive ..................................................54
8.8 CapSense .............................................................55
8.9 Temp Sensor ........................................................55
8.10 DAC ....................................................................55
8.11 Up/Down Mixer ...................................................56
8.12 Sample and Hold ................................................56
9. Programming, Debug Interfaces, Resources ............ 57
9.1 JTAG Interface .....................................................57
9.2 SWD Interface ......................................................59
9.3 Debug Features ....................................................60
9.4 Trace Features .....................................................60
9.5 SWV and TRACEPORT Interfaces ......................60
9.6 Programming Features .........................................60
9.7 Device Security ....................................................60
10. Development Support ............................................... 61
10.1 Documentation ...................................................61
10.2 Online .................................................................61
10.3 Tools ...................................................................61
11. Electrical Specifications ........................................... 62
11.1 Absolute Maximum Ratings ................................62
11.2 Device Level Specifications ................................63
11.3 Power Regulators ...............................................65
11.4 Inputs and Outputs .............................................69
11.5 Analog Peripherals .............................................77
11.6 Digital Peripherals ............................................100
11.7 Memory ............................................................104
11.8 PSoC System Resources .................................108
11.9 Clocking ............................................................111
12. Ordering Information ............................................... 115
12.1 Part Numbering Conventions ...........................116
13. Packaging ................................................................. 117
14. Acronyms ................................................................. 119
15. Reference Documents ............................................. 120
16. Document Conventions .......................................... 121
16.1 Units of Measure ..............................................121
17. Revision History ...................................................... 122
18. Sales, Solutions, and Legal Information ............... 122
Document Number: 001-84932 Rev. **
Page 2 of 122
PRELIMINARY
PSoC
®
5LP: CY8C58LP Family
Datasheet
1. Architectural Overview
Introducing the CY8C58LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5LP platform. The CY8C58LP family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
GPIOs
Sequencer
Usage Example for UDB
4- 25 MHz
( Optional
)
System Wide
Resources
Xtal
Osc
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
CAN
2.0
I2C
Master
/
Slave
SIO
22
Ω
UDB
UDB
Clock Tree
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
12- Bit SPI
UDB
8- Bit
Timer
Logic
UDB
GPIOs
UDB
UDB
UDB
UDB
IMO
4x
Timer
Counter
PWM
FS USB
2.0
USB
PHY
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
32.768 KHz
( Optional
)
RTC
Timer
System Bus
Memory System
WDT
and
Wake
GPIOs
EEPROM
SRAM
CPU System
Cortex M3CPU
Interrupt
Controller
Program &
Debug
Program
Debug &
Trace
EMIF
ILO
FLASH
Cache
Controller
PHUB
DMA
Boundary
Scan
Clocking System
Power Management
System
LCD Direct
Drive
Digital
Filter
Block
Analog System
ADCs
2x
SAR
ADC
+
4x
Opamp
-
SIOs
POR and
LVD
Sleep
Power
1.71 to
5.5 V
1.8 V LDO
SMP
4 x SC / CT Blocks
(TIA, PGA, Mixer etc)
3 per
Opamp
4x DAC
CapSense
1x
Del Sig
ADC
4x
CMP
-
0. 5 to 5.5 V
( Optional
)
Figure 1-1
illustrates the major components of the CY8C58LP
family. They are:
■
■
■
■
■
■
■
■
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Document Number: 001-84932 Rev. **
GPIOs
Temperature
Sensor
+
GPIOs
GPIOs
GPIOs
Page 3 of 122
PRELIMINARY
PSoC
®
5LP: CY8C58LP Family
Datasheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C58LP family, these blocks can include four 16-bit timers,
counters, and PWM blocks; I
2
C slave, master, and multimaster;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the
“Example
Peripherals”
section on page 36 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 36 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
■
■
■
■
■
■
■
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
■
■
■
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
❐
Transimpedance amplifiers
❐
Programmable gain amplifiers
❐
Mixers
❐
Other similar analog components
See the
“Analog Subsystem”
section on page 46 of this
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection.
Two KB of byte-writable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after POR.
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
Digital filter block (DFB)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. One of the ADCs in the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
■
■
■
■
■
Less than 100-µV offset
A gain error of 0.2%
Integral non linearity (INL) less than ±2 LSB
Differential non linearity (DNL) less than ±1 LSB
SINAD better than 84 dB in 16-bit mode
This converter addresses a wide variety of precision analog
applications including some of the most demanding sensors.
The CY8C58LP family also offers up to two SAR ADCs.
Featuring 12-bit conversions at up to 1 M samples per second,
they also offer low nonlinearity and offset errors and SNR better
than 70 dB. They are well-suited for a variety of higher speed
analog applications.
The output of any of the ADCs can optionally feed the
programmable DFB via DMA without CPU intervention. You can
configure the DFB to perform IIR and FIR digital filters and
several user defined custom functions. The DFB can implement
filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
DDIO
pins. Every GPIO
has analog I/O, LCD drive, CapSense, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow V
OH
to be set independently of V
DDIO
when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I
2
C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB, the USB physical
interface is also provided (USBIO). When not using USB, these
pins may also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the
“I/O System and Routing”
section on page 29 of this
datasheet.
Document Number: 001-84932 Rev. **
Page 4 of 122
PRELIMINARY
PSoC
®
5LP: CY8C58LP Family
Datasheet
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has one-percent accuracy at 3 MHz. The IMO
can be configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low-speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in RTC applications. The clocks, together
with programmable clock dividers, provide the flexibility to
integrate most timing requirements.
The CY8C58LP family supports a wide supply operating range
from 1.71 to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or
directly from a wide range of battery types. In addition, it provides
an integrated high efficiency synchronous boost converter that
can power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery.
In addition, you can use the boost converter to generate other
voltages required by the device, such as a 3.3 V supply for LCD
glass drive. The boost’s output is available on the VBOOST pin,
allowing other devices in the application to be powered from the
PSoC.
PSoC supports a wide range of low power modes. These include
a 300-nA hibernate mode with RAM retention and a 2-µA sleep
mode with RTC. In the second mode, the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 3.1 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the
“Power
System”
section on page 24 of this datasheet.
PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for
programming, debug, and test. Using these standard interfaces
you can debug or program the PSoC with a variety of hardware
solutions from Cypress or third party vendors. The Cortex-M3
debug and trace modules include FPB, DWT, ETM, and ITM.
These modules have many features to help solve difficult debug
and trace problems. Details of the programming, test, and
debugging interfaces are discussed in the
“Programming, Debug
Interfaces, Resources”
section on page 57 of this datasheet.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in
Figure 2-3
and
Figure 2-4
show the pins that are
powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in
Figure 2-1.
Figure 2-1. VDDIO Current Limit
I
DDIO X
= 100 mA
V
DDIO X
I/O Pins
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in
Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
V
DDIO X
I/O Pins
PSoC
V
SSD
Document Number: 001-84932 Rev. **
Page 5 of 122
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