CY2410
MPEG Clock Generator with VCXO
Features
■
■
■
■
■
Benefits
■
■
■
■
■
■
■
■
■
■
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
Compatible with MK3727 (–1, –5)
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Application compatibility for a wide variety of designs
Enables design compatibility
Advanced Features
Matches nonlinear MK3727A VCXO control curve (-5)
Digital VCXO control
Electromagnetic interference (EMI) reduction for standards
compliance
Second source for existing designs
VCXO Control
Curve
Other Features
Compatible with MK3727
Matches MK3727A nonlinear
VCXO Control Curve
Part
Number
CY2410–1
CY2410–5
Outputs
1
1
Input Frequency Range
13.5-MHz pullable crystal input per
Cypress specification
13.5-MHz pullable crystal input per
Cypress specification
Output
Frequencies
1 copy of 27 MHz linear
1 copy of 27 MHz nonlinear
CY2410-1, -5 Logic Block Diagram
13.5 XIN
XOUT
OSC
Q
Φ
VCO
P
OUTPUT
DIVIDERS
27 MHz
VCXO
PLL
VDD
VSS
Cypress Semiconductor Corporation
Document #: 38-07317 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 22, 2008
[+] Feedback
CY2410
CY2410-3 Logic Block Diagram
13.5 XIN
XOUT
OSC
Q
Φ
VCO
P
OUTPUT
DIVIDERS
27 MHz
PLL
Digital VCXO
Serial
Programming
Interface
SCLK
SDAT
VDD
VSS
Pin Configuration
Figure 1. CY2410-1, CY2401-5 8-Pin SOIC
XIN
VDD
VCXO
VSS
1
2
3
4
8
7
6
5
XOUT
NC or VSS
NC or VDD
27 MHz
Table 1. Pin Definitions for CY2410–1, –5
Name
X
IN
V
DD
V
CXO
V
SS
27 MHz
NC/V
DD
NC/V
SS
X
OUT[1]
Pin Number
1
2
3
4
5
6
7
8
Description
Reference crystal input
Voltage supply
Input analog control for V
CXO
Ground
27-MHz clock output
No Connect or voltage supply
No Connect or ground
Reference crystal output
Note
1. Float X
OUT
if X
IN
is externally driven.
Document #: 38-07317 Rev. *E
Page 2 of 8
[+] Feedback
CY2410
Pullable Crystal Specifications
[2]
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
Description
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Fundamental mode
Ratio of third overtone mode ESR to fundamental Ratio used because typical
mode ESR
R
1
values are much less than
the maximum spec.
Crystal drive level
Third overtone separation from 3*F
NOM
Third overtone separation from 3*F
NOM
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
No external series resistor
assumed
High side
Low side
Condition
Parallel resonance, funda-
mental mode, AT cut
Min
–
–
–
3
Typ.
13.5
14
–
–
Max
–
–
25
–
Unit
MHz
pF
Ω
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
–
300
–
–
180
14.4
0.5
–
–
–
–
18
2.0
–
–150
7
250
21.6
mW
ppm
ppm
pF
pF
Note
2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
Document #: 38-07317 Rev. *E
Page 3 of 8
[+] Feedback
CY2410
Figure 2. Data Valid and Data Transition Periods
Data Valid
Transition
to next bit
SDAT
t
DH
SCLK
V
IH
V
IL
CLK
HIGH
t
SU
CLK
LOW
Figure 3. Start and Stop Frame
SDAT
SCLK
START
Transition
to next bit
STOP
Figure 4. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
50%
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
t3
80%
CLK
20%
t4
Document #: 38-07317 Rev. *E
Page 4 of 8
[+] Feedback
CY2410
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Supply Voltage
Storage Temperature
[3]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electrostatic Discharge
Description
Min
–0.5
–65
–
V
SS
– 0.3
V
SS
– 0.3
2000
Max
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
°C
°C
V
V
V
Recommended Operating Conditions
Parameter
V
DD
T
A
C
LOAD
f
REF
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
Power up time for V
DD
to reach minimum specified voltage
(power ramp must be monotonic)
Description
Min
3.135
0
–
–
0.05
Typ.
3.3
–
–
13.5
–
Max
3.465
70
15
–
500
Unit
V
°C
pF
MHz
ms
DC Electrical Specifications
Parameter
I
OH
I
OL
C
IN
I
IZ
f
ΔXO
V
VCXO
I
VDD
Name
Output HIGH Current –1,–5
Output LOW Current –1,–5
Input Capacitance
Input Leakage Current
V
CXO
pullability range:–1,–5
V
CXO
input range
Supply Current
Description
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
Min
12
12
–
–
+150
0
–
Typ.
24
24
–
5
–
–
30
Max
–
–
7
–
–
V
DD
35
Unit
mA
mA
pF
μA
ppm
V
mA
AC Electrical Specifications (V
DD
= 3.3V)
[4]
Parameter
[4]
DC
ER
OR
Name
Output Duty Cycle
Rising Edge Rate –1, –5
Description
Duty Cycle is defined in
Figure 4,
50% of V
DD
Output Clock Edge Rate, Measured from
20% to 80% of V
DD
, CLOAD = 15 pF See
Figure 5.
Output Clock Edge Rate, Measured from
80% to 20% of V
DD
, CLOAD = 15 pF See
Figure 5.
Peak-to-peak period jitter
Min
45
0.8
Typ.
50
1.4
Max
55
–
Unit
%
V/ns
ER
OF
Falling Edge Rate –1, –5
0.8
1.4
–
V/ns
t
9
t
10
Clock Jitter –1, –5
PLL Lock Time
–
–
140
–
–
3
ps
ms
Notes
3. Rated for ten years.
4. Not 100% tested.
Document #: 38-07317 Rev. *E
Page 5 of 8
[+] Feedback
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
