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NDB6060L_Q

产品描述MOSFET N-Ch LL FET Enhancement Mode
产品类别半导体    分立半导体   
文件大小357KB,共12页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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NDB6060L_Q概述

MOSFET N-Ch LL FET Enhancement Mode

NDB6060L_Q规格参数

参数名称属性值
产品种类
Product Category
MOSFET
制造商
Manufacturer
Fairchild
RoHSNo
技术
Technology
Si
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TO-263-3
Number of Channels1 Channel
Transistor PolarityN-Channel
Vds - Drain-Source Breakdown Voltage60 V
Id - Continuous Drain Current48 A
Rds On - Drain-Source Resistance25 mOhms
Vgs - Gate-Source Voltage16 V
最小工作温度
Minimum Operating Temperature
- 65 C
最大工作温度
Maximum Operating Temperature
+ 175 C
ConfigurationSingle
Channel ModeEnhancement
系列
Packaging
Reel
系列
Packaging
Cut Tape
Fall Time161 ns
高度
Height
4.83 mm
长度
Length
10.67 mm
Pd-功率耗散
Pd - Power Dissipation
100 W
Rise Time320 ns
工厂包装数量
Factory Pack Quantity
800
Transistor Type1 N-Channel
Typical Turn-Off Delay Time49 ns
Typical Turn-On Delay Time15 ns
宽度
Width
9.65 mm
单位重量
Unit Weight
0.139332 oz

文档预览

下载PDF文档
April 1996
NDP6060L / NDB6060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
Features
48A, 60V. R
DS(ON)
= 0.025
@ V
GS
= 5V.
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25°C unless otherwise noted
NDP6060L
60
60
± 16
± 25
48
144
100
0.67
-65 to 175
275
NDB6060L
Units
V
V
V
Drain-Gate Voltage (R
GS
< 1 M
)
Gate-Source Voltage - Continuous
- Nonrepetitive (t
P
< 50 µs)
Drain Current
- Continuous
- Pulsed
A
P
D
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
W
W/°C
°C
°C
T
J
,T
STG
T
L
Operating and Storage Temperature
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
© 1997 Fairchild Semiconductor Corporation
NDP6060L Rev. D / NDB6060L Rev. E
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