74AHC594-Q100;
74AHCT594-Q100
8-bit shift register with output register
Rev. 2 — 4 July 2013
Product data sheet
1. General description
The 74AHC594-Q100; 74AHCT594-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74AHC594-Q100; 74AHCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out
shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and
STCP) and direct overriding clears (SHR and STR) are provided on both the shift and
storage registers. A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register is always one count pulse ahead of the
storage register.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accept voltages higher than V
CC
Wide supply voltage range from 2.0 V to 5.5 V
8-bit serial-in, parallel-out shift register with storage
Independent direct overriding clears on shift and storage registers
Independent clocks for shift and storage registers
Latch-up performance exceeds 100 mA per JESD78 Class II
Input levels:
For 74AHC594-Q100: CMOS level
For 74AHCT594-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0
)
Multiple package options
Nexperia
74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
3. Applications
Serial-to parallel data conversion
Remote control holding register
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC594-Q100
74AHC594D-Q100
74AHC594DB-Q100
74AHC594PW-Q100
74AHC594BQ-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO16
SSOP16
TSSOP16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
Description
Version
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
SO16
SSOP16
TSSOP16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
74AHCT594-Q100
74AHCT594D-Q100
40 C
to +125
C
74AHCT594DB-Q100
40 C
to +125
C
74AHCT594PW-Q100
40 C
to +125
C
74AHCT594BQ-Q100
40 C
to +125
C
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
74AHC_AHCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
2 of 24
Nexperia
74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
5. Functional diagram
DS
SHCP
SHR
14
11
10
9
12
13
8-BIT STORAGE REGISTER
Q7S
8-STAGE SHIFT REGISTER
STCP
STR
15 1
2
3
4
5
6
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
mbc320
Fig 1.
Functional diagram
SHCP STCP
STR
11
12
9
15
1
2
DS
14
3
4
5
6
7
10
SHR
13
STR
mbc319
mbc322
13
12
10
11
14
R1 SRG8
C1/
1D
R2
C2
STCP
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DS
SHR
SHCP
2D
15
1
2
3
4
5
6
7
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74AHC_AHCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
3 of 24
Nexperia
74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
STAGE 0
DS
D
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
Q
Q7S
FFSH0
CP
R
SHCP
FFSH7
CP
R
SHR
D
Q
D
CP
Q
FFST0
CP
R
STCP
FFST7
R
STR
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mbc321
Fig 4.
Logic diagram
6. Pinning information
6.1 Pinning
Fig 5.
Pin configuration SO16
74AHC_AHCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
4 of 24
Nexperia
74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 6.
Pin configuration (T)SSOP16
Fig 7.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q7S
SHR
SHCP
STCP
STR
DS
Q0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
ground (0 V)
serial data output
shift register reset input (active LOW)
shift register clock input
storage register clock input
storage register reset input (active LOW)
serial data input
parallel data output
supply voltage
74AHC_AHCT594_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2013
5 of 24
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