3kVDC Isolated 1W Single & Dual Output DC/DC Converters
TEMPERATURE DERATING GRAPH
1.5
Output Voltage
TOLERANCE ENVELOPE
5%
2%
Load
Line
Output Power (W)
1.0
0.5
0
-40
85°C
Typic
al
V
NOM
0%
Safe Operating Area
10
25
50
75
-4%
100
100
50
0
Ambient Temperature (°C)
150
Output Load Current (%)
The voltage tolerance envelope shows typical load regulation characteristics for this
product series. The tolerance envelope is the maximum output voltage variation due to
changes in output loading.
TECHNICAL NOTES
ISOLATION VOLTAGE
‘Hi Pot Test’, ‘Flash Tested’, ‘Withstand Voltage’, ‘Proof Voltage’, ‘Dielectric Withstand Voltage’ & ‘Isolation Test Voltage’ are all terms that relate to the same thing, a test voltage,
applied for a specified time, across a component designed to provide electrical isolation, to verify the integrity of that isolation.
Murata Power Solutions MEV1 series of DC/DC converters are all 100% production tested at their stated isolation voltage. This is 3kVDC for 1 minute.
A question commonly asked is, “What is the continuous voltage that can be applied across the part in normal operation?”
The MEV1 has been recognized by Underwriters Laboratory for functional insulation, both input and output should normally be maintained within SELV limits i.e. less than 42.4V
peak, or 60VDC. The isolation test voltage represents a measure of immunity to transient voltages and the part should never be used as an element of a safety isolation system.
The part could be expected to function correctly with several hundred volts offset applied continuously across the isolation barrier; but then the circuitry on both sides of the barrier
must be regarded as operating at an unsafe voltage and further isolation/insulation systems must form a barrier between these circuits and any user-accessible circuitry according
to safety standard requirements.
REPEATED HIGH-VOLTAGE ISOLATION TESTING
It is well known that repeated high-voltage isolation testing of a barrier component can actually degrade isolation capability, to a lesser or greater degree depending on materials,
construction and environment. The MEV1 series has toroidal isolation transformers, with no additional insulation between primary and secondary windings of enameled wire. While
parts can be expected to withstand several times the stated test voltage, the isolation capability does depend on the wire insulation. Any material, including this enamel (typically
polyurethane) is susceptible to eventual chemical degradation when subject to very high applied voltages thus implying that the number of tests should be strictly limited. We
therefore strongly advise against repeated high voltage isolation testing, but if it is absolutely required, that the voltage be reduced by 20% from specified test voltage.
This consideration equally applies to agency recognised parts rated for better than functional isolation where the wire enamel insulation is always supplemented by a further
insulation system of physical spacing or barriers.
SAFETY APPROVAL
The MEV1 series has been recognized by Underwriters Laboratory (UL) to UL 60950 for functional insulation in a maximum still air ambient temperature of 85°C and/or case tem-
perature limit (case temperature measured on the face opposite the pins) as follows:
MEV1SxxxxSC: 130ºC
MEV1SxxxxDC: 130ºC
MEV1DxxxxSC: 94ºC
MEV1DxxxxDC: 96ºC
The MEV1 Series of converters are not internally fused so to meet the requirements of UL 60950 an anti-surge input line fuse should always be used with ratings as defined below.
MEV1x05xxxC: 1A
MEV1x12xxxC: 0.375A
MEV1x15xxxC: 0.375A
MEV1x24xxxC: 0.2A
MEV1x48xxxC: 0.1A
All fuses should be UL recognized and rated to at least the maximum allowable DC input voltage.
File number E151252 applies.
RoHS COMPLIANT INFORMATION
This series is compatible with RoHS soldering systems with a peak wave solder temperature of
260°C for 10 seconds. The pin termination finish on the SIP package type is Tin Plate, Hot Dipped
over Matte Tin with Nickel Preplate. The DIP types are Matte Tin over Nickel Preplate. Both types in
this series are backward compatible with Sn/Pb soldering systems.
For further information, please visit www.murata-ps.com/rohs
www.murata-ps.com/support
KDC_MEV1.F06
Page 4 of 10
MEV1 Series
3kVDC Isolated 1W Single & Dual Output DC/DC Converters
APPLICATION NOTES
Minimum load
The minimum load to meet datasheet specification is 10% of the full rated load across the specified input voltage range. Lower than 10% minimum loading will result in
an increase in output voltage, which may rise to typically double the specified output voltage if the output load falls to less than 5%.
Capacitive loading and start up
Typical start up times for this series, with a typical input voltage rise time of 2.2μs and output capacitance of 10μF, are shown in the table below. The product
series will start into a capacitance of 47μF with an increased start time, however, the maximum recommended output capacitance is 10μF.
Start-up time
μs
585
1550
2700
4320
605
1750
3000
4800
660
1720
Start-up time
μs
3045
4445
440
4355
1855
2930
580
1320
2075
3235
Typical Start-Up Wave Form
MEV1x0505xC
MEV1x0509xC
MEV1x0512xC
MEV1x0515xC
MEV1x1205xC
MEV1x1209xC
MEV1x1212xC
MEV1x1215xC
MEV1x1505xC
MEV1x1509xC
MEV1x1512xC
MEV1x1515xC
MEV1x2405xC
MEV1x2409xC
MEV1x2412xC
MEV1x2415xC
MEV1x4805SC
MEV1x4809SC
MEV1x4812SC
MEV1x4815SC
Ripple & Noise Characterisation Method
Ripple and noise measurements are performed with the following test configuration.
1μF X7R multilayer ceramic capacitor, voltage rating to be a minimum of 3 times the output voltage of the DC/DC converter
10μF tantalum capacitor, voltage rating to be a minimum of 1.5 times the output voltage of the DC/DC converter with an ESR of less
C2
than 100mΩ at 100 kHz
C3
100nF multilayer ceramic capacitor, general purpose
R1
450Ω resistor, carbon film, ±1% tolerance
R2
50Ω BNC termination
T1
3T of the coax cable through a ferrite toroid
RLOAD
Resistive load to the maximum power rating of the DC/DC converter. Connections should be made via twisted wires
Measured values are multiplied by 10 to obtain the specified values.
FPGA/CPLD
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