Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
FEATURES
•
4-bit parallel load shift register
•
Independent 3-State buffer outputs, Q0–Q3
•
Separate Qs output for serial expansion
•
Asynchronous Master Reset
DESCRIPTION
The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0!Q1!Q2!Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.
The Master Reset (MR) is an asynchronous active-Low input. When
Low, the MR overrides the clock and all other inputs and clears the
register.
The 3-state output buffers are designed to drive heavily loaded
3-State buses, or large capacitive loads.
The active-Low Output Enable (OE) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.
PIN CONFIGURATION
MR
Ds
D0
D1
D2
D3
PE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q0
Q1
Q2
Q3
Qs
CP
OE
SF00940
TYPE
74F395
TYPICAL f
MAX
120MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
32mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F395N
N74F395D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D3
Ds
PE
MR
OE
CP
Qs
Q0–Q3
Data inputs
Serial data input
Parallel Enable input
Master Reset input (active Low)
Output Enable input (active Low)
Clock Pulse input (active falling edge)
Serial expansion output
Data outputs (3-State)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
3.0mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1990 Oct 23
1
853–0370 00780
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
LOGIC SYMBOL
2
3
4
5
6
IEC/IEEE SYMBOL (IEEE/IEC)
1
9
R
EN4
M1[LOAD]
M2[SHIFT]
10
C3/2!
2,3D
1,3D
1,3D
4
4
14
13
12
11
15
SRG4
Ds
7
10
9
1
PE
CP
OE
MR
Q0
D0
D1
D2
D3
7
Qs
11
2
3
Q1
Q2
Q3
4
5
15
V
CC
= Pin 16
GND = Pin 8
14
13
12
6
SF00941
SF00942
LOGIC DIAGRAM
OE
CP
MR
PE
9
10
1
7
Ds
2
CP
R
S
CLR
Q
D0
3
Q
15
Q0
CP
4
R
S
CLR
Q
D1
Q
14
Q1
CP
5
R
S
CLR
Q
D2
Q
13
Q2
CP
6
R
S
CLR
Q
D3
Q
12
Q3
11
V
CC
= Pin 16
GND = Pin 8
Qs
SF00943
1990 Oct 23
2
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
MODE SELECT–FUNCTION TABLE
INPUTS
MR
L
H
H
H
H
#
#
#
CP
X
#
PE
X
l
l
h
h
Ds
X
l
h
X
X
Dn
X
X
X
l
h
Q0
L
L
H
L
H
OUTPUTS
Q1
L
q0
q0
L
H
Q2
L
q1
q1
L
H
Q3
L
q2
Shift right
q2
L
Parallel load
H
3-STATE BUFFER
OPERATING
MODES
Read
L
H
H
H
L
H
H
Z
Z
H
L
Disable buffers
H
REGISTER
OPERATING
MODES
Reset (clear)
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low
clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low
clock transition
qn = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the High-to-Low clock
transition
X = Don’t care
Z = High impedance “OFF” state
#
= High-to-Low clock transition
INPUTS
OE
L
Qn (Register)
L
OUTPUTS
Q0, Q1, Q2, Q3
L
Qs
L
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Qs
Current applied to output in Low output state
Q0–Q3
Operating free-air temperature range
Storage temperature range
48
0 to +70
–65 to +150
mA
°C
°C
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +5.5
40
UNIT
V
V
mA
V
mA
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
Qs
High-level output current
Q0–Q3
Qs
I
OL
T
amb
Low-level output current
Q0–Q3
Operating free-air temperature range
0
24
70
mA
°C
–3
20
mA
mA
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
NOM
5.0
MAX
5.5
V
V
V
mA
mA
UNIT
1990 Oct 23
3
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
±10%V
CC
I
OL
= MAX
±5%V
CC
LIMITS
MIN
2.5
2.7
2.4
2.7
0.35
0.35
–0.73
0.50
0.50
–1.2
100
20
–0.6
50
–50
–60
MR=PE=Dn=Ds=4.5V,
OE=GND, CP=#
V
CC
= MAX
MR=OE=Dn=Ds=GND,
PE=4.5V, CP=#
MR=Dn=Ds=GND,
OE=4.5V
33
35
32
–150
48
50
46
3.4
TYP
2
MAX
UNIT
V
V
V
V
V
V
V
µA
µA
mA
µA
µA
mA
mA
mA
mA
Qs
V
OH
High-level output voltage
Q0–Q3
V
CC
= MIN,
V
IL
= MAX,
V
IH
=MIN
I
OH
=–1mA
I
OH
=–3mA
V
OL
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
Low-level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Off-state output current High
level of voltage applied
Off-state output current Low
level of voltage applied
Short-circuit output current
3
I
CCH
Q0–Q3
only
Q0–Q3
only
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN,
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.7V
V
CC
= MAX, V
O
= 0.5V
V
CC
= MAX
I
CC
Supply current (total)
I
CCL
I
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1990 Oct 23
4
Philips Semiconductors
Product specification
4-bit cascadable shift register (3-State)
74F395
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency
Propagation delay
CP to Qn
Propagation delay
CP to Qs
Propagation delay
MR to Qn
Propagation delay
MR to Qs
Output Enable time
to High or Low level
Output Disable time
from High or Low level
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 2
Waveform 4
Waveform 5
Waveform 4
Waveform 5
105
3.5
5.0
4.5
5.5
5.0
4.5
4.0
3.5
1.0
1.0
TYP
120
6.0
8.0
6.0
7.5
7.5
7.0
6.5
6.0
2.5
3.5
8.5
11.0
8.5
10.0
10.0
9.0
9.0
8.0
4.5
5.5
3.5
5.0
4.0
5.0
5.0
4.5
4.0
3.5
1.0
1.0
9.5
11.5
9.5
10.5
10.5
9.5
10.0
8.5
5.5
6.5
MAX
V
CC
= +5V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
MAX
MHz
ns
ns
ns
ns
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
Setup time, High or Low
PE to CP
Hold time, High or Low
PE to CP
CP Pulse width
High or Low
MR Pulse width
Low
Recovery time
MR to CP
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 1
Waveform 2
Waveform 2
2.5
1.5
1.5
1.5
6.5
6.0
0
0
5.0
4.0
2.5
6.0
TYP
MAX
V
CC
= +5V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
3.0
2.0
1.5
1.5
7.0
6.5
0
0
5.5
4.5
3.0
7.0
MAX
ns
ns
ns
ns
ns
ns
ns
UNIT
1990 Oct 23
5
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