DATA SHEET
2GB Registered DDR2 SDRAM DIMM
EBE21RD4AGFA (256M words
×
72 bits, 2 Ranks)
Description
The EBE21RD4AGFA is a 256M words
×
72 bits, 2
ranks DDR2 SDRAM Module, mounting 36 pieces of
512M bits DDR2 SDRAM sealed in FBGA (µBGA
)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
•
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
•
Power supply: VDD
=
1.8V
±
0.1V
•
Data rate: 667Mbps/533Mbps/400Mbps (max.)
•
SSTL_18 compatible I/O
•
Double-data-rate architecture: two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
referenced to both edges of DQS
•
Four internal banks for concurrent operation
(components)
•
Burst length: 4, 8
•
/CAS latency (CL): 3, 4, 5
•
Auto precharge option for each burst access
•
Auto refresh and self refresh modes
•
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
/DQS can be disabled for single-ended Data Strobe
operation
•
1 piece of PLL clock driver, 4 piece of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0794E20 (Ver. 2.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2005
EBE21RD4AGFA
Pin Description
Pin name
A0 to A13
A10 (AP)
BA0, BA1
DQ0 to DQ63
CB0 to CB7
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CK0
/CK0
DQS0 to DQS17, /DQS0 to /DQS17
SCL
SDA
SA0 to SA2
VDD
VDDSPD
VREF
VSS
ODT0, ODT1
/RESET
Par_In*
2
2
Function
Address input
Row address
Column address
Auto precharge
Bank select address
Data input/output
Check bit (Data input/output)
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for serial EEPROM
Input reference voltage
Ground
ODT control
Reset pin (forces register and PLL inputs low) *
Parity bit for the address and control bus
Parity error found on the address and control bus
No connection
1
A0 to A13
A0 to A9, A11
Err_Out*
NC
Notes: 1. Reset pin is connected to both OE of PLL and reset to register.
2. NC/Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and
command parity.
Data Sheet E0794E20 (Ver. 2.0)
4
EBE21RD4AGFA
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM ranks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
Bit5
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
Bit4
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
1
0
1
Bit3
0
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
Bit2
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
Bit1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Bit0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
Hex value
80H
08H
08H
0EH
0BH
61H
48H
00H
05H
30H
3DH
50H
45H
50H
60H
02H
82H
04H
04H
00H
0CH
04H
38H
01H
01H
00H
03H
3DH
50H
50H
60H
50H
60H
3CH
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
11
2
72
0
SSTL 1.8V
3.0ns*
1
Voltage interface level of this assembly 0
DDR SDRAM cycle time, CL = 5
-6E
-5C
-4A
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.75ns*
5.0ns*
1
1
10
SDRAM access from clock (tAC)
-6E
-5C
-4A
0.45ns*
0.5ns*
0.6ns*
ECC
7.8µs
×
4
×
4
0
4,8
4
3, 4, 5
1
1
1
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
DIMM Mechanical Characteristics
DIMM type information
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 4
-6E, -5C
-4A
Maximum data access time (tAC) from
clock at CL = 4
-6E, -5C
-4A
4.00mm max.
Registered
Normal
Weak Driver
50Ω ODT Support
3.75ns*
5.0ns*
0.5ns*
0.6ns*
5.0ns*
0.6ns*
15ns
1
1
24
1
1
1
25
26
27
Minimum clock cycle time at CL = 3
Maximum data access time (tAC) from
clock at CL = 3
Minimum row precharge time (tRP)
1
Data Sheet E0794E20 (Ver. 2.0)
5
stm32/stm8
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