CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
36-Mbit (1M × 36/2M × 18)
Pipelined Sync SRAM (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined Sync SRAM (With ECC)
Features
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Functional Description
The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 SRAM
integrate 1M × 36/2M × 18/1M × 36 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
X
and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle. This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The
CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Supports bus operation up to 250 MHz
Available speed grades are 250 MHz and 167 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply
2.5 V or 3.3 V I/O power supply
Fast clock-to-output time
❐
2.5 ns (for 250 MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1440KV33, CY7C1442KV33 and CY7C1440KVE33 are
available in Pb-free 100-pin TQFP, and Pb-free and non Pb-free
165-ball FBGA packages.
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
On-Chip error correction code (ECC) to reduce soft error rate
(SER)
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Selection Guide
Description
Maximum access time
Maximum operating current
× 18
× 36
250 MHz
2.5
220
240
167 MHz
3.4
Not Offered
190
Unit
ns
mA
Cypress Semiconductor Corporation
Document Number: 001-66676 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 5, 2016
CY7C1440KV33
CY7C1442KV33
CY7C1440KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
On-Chip ECC .............................................................. 9
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC®Solutions ....................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Document Number: 001-66676 Rev. *G
Page 4 of 33
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