19-5005; Rev 0; 10/09
EVALUATION KIT AVAILABLE
General Description
The MAX3624A is a low-jitter, precision clock generator
optimized for networking applications. The device inte-
grates a crystal oscillator and a phase-locked loop (PLL)
clock multiplier to generate high-frequency clock outputs
for Ethernet, Fibre Channel, SONET/SDH, and other
networking applications.
This proprietary PLL design features ultra-low jitter
(0.36psRMS) and excellent power-supply noise rejection,
minimizing design risk for network equipment.
The MAX3624A has three LVPECL outputs and one
LVCMOS output. Selectable output dividers and a
selectable feedback divider allow a range of output
frequencies.
Features
♦
Crystal Oscillator Interface: 19.375MHz to 27MHz
♦
CMOS Input: 19MHz to 40.5MHz
♦
Output Frequencies
Ethernet: 62.5MHz, 125MHz, 156.25MHz,
312.5MHz
Fibre Channel: 106.25MHz, 159.375MHz,
212.5MHz, 318.75MHz
SONET/SDH: 77.76MHz, 155.52MHz, 311.04MHz
♦
Low Jitter
0.14ps
RMS
(1.875MHz to 20MHz)
0.36ps
RMS
(12kHz to 20MHz)
♦
Excellent Power-Supply Noise Rejection
♦
No External Loop Filter Capacitor Required
MAX3624A
Applications
Ethernet Networking Equipment
Fibre Channel Storage Area Network
SONET/SDH Network
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
Ordering Information
PART
MAX3624AETJ+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Block Diagram
IN_SEL
MR
BYPASS
SELA[1:0]
QAC_OE
LVCMOS
BUFFER
RESET LOGIC/POR
RESET
DIVIDER
NA
LVPECL
BUFFER
QA_C
SELA[1:0]
SELB[1:0]
FB_SEL[1:0]
BYPASS
QA_OE
QA
QA
RESET
LVCMOS
REF_IN
27pF
X_IN
CRYSTAL
OSCILLATOR
X_OUT
33pF
DIVIDERS:
M = 16, 24, 25, 32
NA = 1, 2, 3, 4, 5, 6, 8, 10, 12
NB = 1, 2, 3, 4, 5, 6, 8, 10, 12
DIVIDER
M
DIVIDER
NB
1
0
PFD
FILTER
RESET
620MHz TO 648MHz
VCO
1
RESET
0
QB1_OE
LVPECL
BUFFER
QB1
QB1
QB0_OE
LVPECL
BUFFER
QB0
QB0
MAX3624A
FB_SEL[1:0]
SELB[1:0]
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter, Precision Clock Generator
with Four Outputs
MAX3624A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range V
CC
, V
CCA
,
V
DDO_A
, V
CCO_A
, V
CCO_B
................................-0.3V to +4.0V
Voltage Range at REF_IN, IN_SEL,
FB_SEL[1:0], SELA[1:0], SELB[1:0],
QAC_OE, QA_OE, QB0_OE, QB1_OE,
MR,
BYPASS
..........................................-0.3V to (V
CC
+ 0.3V)
Voltage Range at X_IN ..........................................-0.3V to +1.2V
Voltage Range at GNDO_A...................................-0.3V to +0.3V
Voltage Range at X_OUT ............................-0.3V to (V
CC
- 0.6V)
Current into QA_C ...........................................................±50mA
Current into QA,
QA,
QB0,
QB0,
QB1,
QB1
.....................-56mA
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
PARAMETER
Power-Supply Current
SYMBOL
I
CC
(Note 4)
CONDITIONS
MIN
TYP
82
MAX
100
UNITS
mA
CONTROL INPUT CHARACTERISTICS
(SELA[1:0], SELB[1:0], FB_SEL[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR,
BYPASS
Pins)
Input Capacitance
Input Pulldown Resistor
Input Logic Bias Resistor
Input Pullup Resistor
C
IN
R
PULLDOWN
Pins MR, FB_SEL[1:0]
R
BIAS
R
PULLUP
Pins SELA[1:0], SELB[1:0], QB0_OE
Pins QAC_OE, QA_OE, QB1_OE, IN_SEL,
BYPASS
V
CC
-
1.18
V
CC
-
1.90
(Note 2)
20% to 80% (Note 2)
PLL enabled
PLL bypassed (Note 5)
0.6
200
48
45
2
75
50
75
pF
k
k
k
LVPECL OUTPUT SPECIFICATIONS (QA,
QA,
QB0,
QB0,
QB1,
QB1
Pins)
Output High Voltage
Output Low Voltage
Peak-to-Peak Output-Voltage
Swing (Single-Ended)
Clock Output Rise/Fall Time
Output Duty-Cycle Distortion
V
OH
V
OL
V
CC
-
0.98
V
CC
-
1.7
0.72
350
50
50
V
CC
-
0.83
V
CC
-
1.55
0.9
600
52
55
V
V
V
P-P
ps
%
LVCMOS/LVTTL INPUT SPECIFICATIONS
(SELA[1:0], SELB[1:0], FB_SEL[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR,
BYPASS
Pins)
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
-80
2.0
0.8
80
V
V
μA
μA
2
_______________________________________________________________________________________
Low-Jitter, Precision Clock Generator
with Four Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless other-
wise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
PLL enabled
PLL bypassed
V
IH
V
IL
I
IH
I
IL
V
IN
= V
CC
V
IN
= 0V
PLL enabled
-240
30
2.5
V
OH
V
OL
QA_C sourcing 12mA
QA_C sinking 12mA
(Notes 3 and 6)
PLL enabled
PLL bypassed (Note 5)
250
42
40
500
50
50
14
620
RJ
RMS
12kHz to 20MHz
1.875MHz to 20MHz
LVPECL output
LVCMOS output
(Note 11)
0.36
0.14
-59
-47
4.6
-70
Between QB0 and QB1
Output Skew
Between QA and QB0 or QB1,
PECL outputs
f = 1kHz
Clock Output SSB Phase Noise
at 125MHz (Note 12)
f = 10kHz
f = 100kHz
f = 1MHz
f > 10MHz
15
20
-124
-125
-130
-145
-153
dBc/Hz
ps
648
1.0
MHz
ps
RMS
dBc
ps
P-P
dBc
2.6
0.4
1000
58
60
70
2.0
0.8
240
CONDITIONS
MIN
TYP
MAX
40.5
320
UNITS
MAX3624A
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
Reference Clock Frequency
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
Reference Clock Duty Cycle
Input Capacitance
QA_C SPECIFICATIONS
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
Output Duty-Cycle Distortion
Output Impedance
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range
Random Jitter (Note 7)
Spurs Induced by Power-Supply
Noise (Notes 8, 9, 10)
Deterministic Jitter Induced by
Power-Supply Noise
Nonharmonic and Subharmonic
Spurs
V
V
ps
%
MHz
V
V
μA
μA
%
pF
Note 1:
Note 2:
Note 3:
Note 4:
A series resistor of up to 10.5Ω is allowed between V
CC
and V
CCA
for filtering supply noise when system power-supply tol-
erance is V
CC
= 3.3V ±5%. See Figure 2.
Guaranteed up to 320MHz for LVPECL output.
Guaranteed up to 160MHz for LVCMOS output.
All outputs enabled and unloaded. IN_SEL set high.
_______________________________________________________________________________________
3
Low-Jitter, Precision Clock Generator
with Four Outputs
MAX3624A
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C unless other-
wise noted.) (Notes 1, 2, and 3)
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Measured with crystal or AC-coupled, 50% duty-cycle signal on REF_IN.
Measured using setup shown in Figure 1 with V
CC
= 3.3V ±5%.
Measured with crystal source.
Measured with 40mV
P-P
, 100kHz sinusoidal signal on the supply.
Measured at 156.25MHz output.
Measured using setup shown in Figure 2.
Calculated based on measured spurs induced by power-supply noise (refer to Application Note 4461:
HFAN-04.5.5:
Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers).
Note 12:
Measured with 25MHz crystal or 25MHz reference clock at LVCMOS input with a slew rate of 0.5V/ns or greater.
MAX3624A
QA_C
36Ω
499Ω
4.7pF
0.1μF
Z
0
= 50Ω
OSCILLOSCOPE
50Ω
Figure 1. LVCMOS Output Measurement Setup
4
_______________________________________________________________________________________
Low-Jitter, Precision Clock Generator
with Four Outputs
Typical Operating Characteristics
(Typical values are at V
CC
= +3.3V, T
A
= +25°C, crystal frequency = 25MHz.)
MAX3624A
SUPPLY CURRENT
vs. TEMPERATURE
MAX3624A toc01
DIFFERENTIAL OUTPUT WAVEFORM
AT 156.25MHz (LVPECL OUTPUT)
MAX3624A toc02
OUTPUT WAVEFORM AT 125MHz
(LVCMOS OUTPUT)
MAX3624A toc03
250
225
200
SUPPLY CURRENT (mA)
175
150
125
100
75
50
25
0
-40
-15
10
35
60
ALL OUTPUTS ACTIVE AND UNTERMINATED
ALL OUTPUTS ACTIVE AND TERMINATED
MEASURED USING 50Ω OSCILLOSCOPE INPUT
THROUGH NETWORK SHOWN IN FIGURE 1
AMPLITUDE (200mv/div)
AMPLITUDE (50mV/div)
1ns/div
85
1ns/div
AMBIENT TEMPERATURE (°C)
PHASE NOISE AT 312.5MHz
CLOCK FREQUENCY
MAX3624A toc04
PHASE NOISE AT 125MHz
CLOCK FREQUENCY
MAX3624A toc05
PHASE NOISE AT 212.5MHz
CLOCK FREQUENCY
(26.5625MHz CRYSTAL)
-90
-100
-110
-120
-130
-140
-150
-160
MAX3624A toc06
-80
NOISE POWER DENSITY (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
0.1
1
10
100
-80
NOISE POWER DENSITY (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
-80
NOISE POWER DENSITY (dBc/Hz)
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
NOISE SPUR AMPLITUDE
vs. NOISE FREQUENCY
-10
SPUR AMPLITUDE (dBc)
-20
-30
-40
-50
-60
-70
-80
-90
10
100
1000
10,000
NOISE FREQUENCY (kHz)
f
C
= 156.25MHz
NOISE AMPLITUDE = 40mV
P-P
MAX3624A toc07
0
_______________________________________________________________________________________
5
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