MR2A08A
FEATURES
• Fast 35ns Read/Write Cycle
• SRAM Compatible Timing, Uses Existing SRAM Controllers Without
Redesign
• Unlimited Read & Write Endurance
• Data Always Non-volatile for >20 years at Temperature
• One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in
System for Simpler, More Efficient Design
• Replace battery-backed SRAM solutions with MRAM to eliminate
battery assembly, improving reliability
• 3.3 Volt Power Supply
• Automatic Data Protection on Power Loss
• Commercial, Industrial, Automotive Temperatures
•
RoHS-Compliant SRAM TSOP2 Package
•
RoHS-Compliant SRAM BGA Package
• AEC-Q100 Grade 1 Qualified
512K x 8 MRAM Memory
RoHS
INTRODUCTION
The MR2A08A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as
524,288 words of 8 bits. The MR2A08A offers SRAM compatible 35ns read/write timing with unlimited
endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power
loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
The MR2A08A is the ideal memory solution for applications that must permanently store and retrieve criti-
cal data and programs quickly.
The MR2A08A is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type 2 package
or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are
compatible with similar low-power SRAM products and other non-volatile RAM products.
The MR2A08A provides highly reliable data storage over a wide range of temperatures. The product is of-
fered with commercial temperature range (0 to +70 °C), industrial temperature range (-40 to +85 °C), and
AEC-Q100 Grade 1 temperature range (-40 to +125 °C) options.
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 2
2. ELECTRICAL SPECIFICATIONS................................................................. 4
3. TIMING SPECIFICATIONS.......................................................................... 7
4. ORDERING INFORMATION....................................................................... 11
5. MECHANICAL DRAWING.......................................................................... 12
6. REVISION HISTORY...................................................................................... 14
How to Reach Us.......................................................................................... 14
Copyright © 2015 Everspin Technologies, Inc.
1
MR2A08A Rev. 6.2, 6/2015
MR2A08A
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
G
OUTPUT
ENABLE
BUFFER
9
10
ROW
DECODER
COLUMN
DECODER
OUTPUT ENABLE
A[18:0]
19
ADDRESS
BUFFER
E
CHIP
ENABLE
BUFFER
8
512k x 8
BIT
MEMORY
ARRAY
8
SENSE
AMPS
8
OUTPUT
BUFFER
8
W
WRITE
ENABLE
BUFFER
FINAL
WRITE
DRIVERS
8
WRITE
DRIVER
8
DQ[7:0]
WRITE ENABLE
Table 1.1 Pin Functions
Signal Name
A
E
W
G
DQ
V
DD
V
SS
DC
NC
Function
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
Power Supply
Ground
Do Not Connect
No Connection - Pin 2, 43 (TSOPII); Ball H6, G2 (BGA) Reserved For Future Expansion
Copyright © 2015 Everspin Technologies, Inc.
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MR2A08A Rev. 6.2, 6/2015
DEVICE PIN ASSIGNMENT
MR2A08A
Figure 1.2 Pin Diagrams for Available Packages (Top View)
DC
NC
A
A
A
A
A
E
DQ
DQ
V
DD
V
SS
DQ
DQ
W
A
A
A
A
A
DC
DC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC
NC
DC
A
A
A
A
G
DQ
DQ
V
SS
V
DD
DQ
DQ
DC
A
A
A
A
A
DC
DC
1
DC
NC
DQ
2
G
DC
NC
DQ
DQ
3
A
A
A
A
DC
A
A
A
4
A
A
A
A
A
A
A
A
5
A
E
NC
DQ
DQ
6
DC
DC
DQ
A
B
C
D
E
F
G
H
V
SS
V
DD
DQ
V
DD
V
SS
DQ
NC
NC
A
NC
W
A
NC
A
NC
NC
44 Pin TSOP2
48 Pin FBGA
Table 1.2 Operating Modes
E
1
H
L
L
L
1
2
G
1
X
H
L
X
W
1
X
H
H
L
Mode
Not selected
Output disabled
Byte Read
Byte Write
V
DD
Current
I
SB1
, I
SB2
I
DDR
I
DDR
I
DDW
DQ[7:0]
2
Hi-Z
Hi-Z
D
Out
D
in
H = high, L = low, X = don’t care
Hi-Z = high impedance
Copyright © 2015 Everspin Technologies, Inc.
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MR2A08A Rev. 6.2, 6/2015
MR2A08A
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field
more intense than the maximum field intensity specified in the maximum ratings.
Table 2.1 Absolute Maximum Ratings
1
Symbol
V
DD
V
IN
I
OUT
P
D
Parameter
Supply voltage
2
Voltage on any pin
2
Output current per pin
Package power dissipation
3
Temp Range
-
-
-
-
Commercial
Package
-
-
Value
-0.5 to 4.0
-0.5 to V
DD
+ 0.5
±20
0.600
-10 to 85
-45 to 95
-45 to 130
-55 to 150
260
2,000
2,000
10,000
2,000
8,000
8,000
10,000
8,000
Unit
V
V
mA
W
-
Note 3
-
-
-
-
-
TSOP2, BGA
BGA
TSOP2
TSOP2
TSOP2, BGA
BGA
TSOP2
TSOP2
T
BIAS
Temperature under bias
Industrial
AEC-Q100 Grade 1
°C
T
stg
T
Lead
Storage Temperature
Lead temperature during solder
(3 minute max)
-
-
Commercial
°C
°C
H
max_write
Maximum magnetic field during
write
Industrial
AEC-Q100 Grade 1
Commercial
A/m
H
max_read
Maximum magnetic field during
read or standby
Industrial
AEC-Q100 Grade 1
A/m
Notes:
1.
2.
3.
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted
to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.
All voltages are referenced to V
SS
.
Power dissipation capability depends on package characteristics and use environment.
Copyright © 2015 Everspin Technologies, Inc.
4
MR2A08A Rev. 6.2, 6/2015
Electrical Specifications
Table 2.2 Operating Conditions
Parameter
Power supply voltage
1
Write inhibit voltage
Input high voltage
Input low voltage
Temperature under bias
MR2A08A (Commercial)
MR2A08AC (Industrial)
MR2A08AM (AEC-Q100 Grade 1)
4
1
2
MR2A08A
Symbol
V
DD
V
WI
V
IH
V
IL
Min
3.0
2.5
2.2
-0.5
3
0
-40
-40
Typical
3.3
2.7
-
-
Max
3.6
3.0
1
V
DD
+ 0.3
2
0.8
70
85
125
Unit
V
V
V
V
T
A
°C
There is a 2 ms startup time once V
DD
exceeds V
DD,
(min). See Power
Up and Power Down Sequencing
below.
V
IH
(max) = V
DD
+ 0.3 V
DC
; V
IH
(max) = V
DD
+ 2.0 V
AC
(pulse width ≤ 10 ns) for I ≤ 20.0 mA.
3
V
IL
(min) = -0.5 V
DC
; V
IL
(min) = -2.0 V
AC
(pulse width ≤ 10 ns) for I ≤ 20.0 mA.
4
AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life)
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever V
DD
is less than V
WI
. As soon as V
DD
exceeds V
DD
(min), there is a
startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize.
The
E
and
W
control signals should track V
DD
on power up to V
DD
- 0.2 V or V
IH
(whichever is lower) and remain high
for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal
remains high if the driving signal is Hi-Z during power up. Any logic that drives
E
and
W
should hold the signals high
with a power-on reset signal for longer than the startup time.
During power loss or brownout where V
DD
goes below V
WI
, writes are protected and a startup time must be observed
when power returns above V
DD
(min).
Figure 2.1 Power Up and Power Down Diagram
V
WI
V
DD
BROWNOUT or POWER LOSS
2 ms
STARTUP
2 ms
RECOVER
NORMAL
OPERATION
READ/WRITE
INHIBITED
NORMAL
OPERATION
READ/WRITE
INHIBITED
V
IH
V
IH
E
W
Copyright © 2015 Everspin Technologies, Inc.
5
MR2A08A Rev. 6.2, 6/2015
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