NB7V32M
1.8V / 2.5V, 10GHz
÷2
Clock
Divider with CML Outputs
Multi−Level Inputs w/ Internal
Termination
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Description
The NB7V32M is a differential
B2
Clock divider with
asynchronous reset. The differential Clock inputs incorporate internal
50
W
termination resistors and will accept LVPECL, CML and LVDS
logic levels.
The NB7V32M produces a
B2
output copy of an input Clock
operating up to 10 GHz with minimal jitter.
The RESET Pin is asserted on the rising edge. Upon power−up, the
internal flip−flops will attain a random state; the Reset allows for the
synchronization of multiple NB7V32M’s in a system.
The 16 mA differential CML output provides matching internal
50
W
termination which guarantees 400 mV output swing when
externally receiver terminated with 50
W
to V
CC
.
The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M
(2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16−pin
QFN package. The NB7V32M is a member of the GigaComm™
family of high performance clock products. Application notes,
models, and support documentation are available at
www.onsemi.com.
Features
MARKING
DIAGRAM*
1
1
QFN−16
MN SUFFIX
CASE 485G
16
NB7V
32M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 10 GHz, typical
Random Clock Jitter < 0.8 ps RMS
200 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Operating Range: V
CC
= 1.71 V to 2.625 V with GND = 0 V
Internal 50
W
Input Termination Resistors
QFN−16 Package, 3 mm x 3 mm
−40°C
to +85°C Ambient Operating Temperature
These are Pb−Free Devices
R
RESET
VTCLK
50W
CLK
Q
Q
B2
CLK
50W
VTCLK
VREFAC
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
August, 2010
−
Rev. 5
1
Publication Order Number:
NB7V32M/D
NB7V32M
VCC
16
VTCLK 1
CLK
CLK
2
NB7V32M
3
10
9
5
6
7
8
Q
VCC
R
15
VCC VCC
14
13
12
11
VCC
Q
Exposed Pad (EP)
Table 1. TRUTH TABLE
CLK
x
Z
CLK
x
W
R
H
L
Q
L
CLK
B
2
Q
H
CLK
B
2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
VTCLK 4
VREFAC GND GND GND
Figure 2. Pin Configuration
(Top View)
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
VTCLK
CLK
CLK
VTCLK
VREFAC
GND
GND
GND
VCC
Q
Q
VCC
VCC
VCC
R
VCC
EP
I/O
−
LVPECL, CML,
LVDS Input
LVPECL, CML,
LVDS Input
−
−
−
−
−
−
CML Output
CML Output
−
−
−
LVCMOS Input
−
−
Internal 50
W
Termination Pin for CLK
Non−inverted Differential CLK Input. (Note 1)
Inverted Differential CLK Input. (Note 1)
Internal 50
W
Termination Pin for CLK
Internally Generated Output Voltage Reference for Capacitor−Coupled Inputs, only
Negative Supply Voltage
Negative Supply Voltage
Negative Supply Voltage
Positive Supply Voltage. (Note 2)
Inverted Differential Output
Non−Inverted Differential Output
Positive Supply Voltage. (Note 2)
Positive Supply Voltage. (Note 2)
Positive Supply Voltage. (Note 2)
Asynchronous Reset Input. Internal 75 kW pulldown to GND.
Positive Supply Voltage. (Note 2)
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for im-
proved heat transfer out of package. The exposed pad must be attached to a heat−sinking con-
duit. The pad is electrically connected to the die, and must be electrically and thermally connected
to GND on the PC board.
Description
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50
W
source
termination resistors.
2. VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7V32M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Moisture Sensitivity
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
16−QFN
Oxygen Index: 28 to 34
Value
> 4 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
164
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
INPP
I
IN
I
OUT
I
VREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input Voltage
Differential Input Voltage |D
−
D|
Input Current Through R
T
(50
W
Resistor)
Output Current Through R
T
(50
W
Resistor)
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 3)
Thermal Resistance (Junction−to−Case)
(Note 3)
Wave Solder Pb−Free
0 lfpm
500 lfpm
QFN−16
QFN−16
QFN−16
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
3.0
−0.5
to V
CC
+ 0.5 V
1.89
$40
$40
$1.5
−40
to +85
−65
to +150
42
35
4
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7V32M
Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT
V
CC
= 1.71 V to 2.625 V; GND = 0 V; T
A
=
−40°C
to 85°C (Note 4)
Symbol
POWER SUPPLY CURRENT
I
CC
Power Supply Current (Inputs and Outputs Open)
V
CC
= 2.5 V
$
5%
V
CC
= 1.8 V
$
5%
90
80
100
90
mA
Characteristic
Min
Typ
Max
Unit
CML OUTPUTS
V
OH
Output HIGH Voltage (Note 5)
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 1.8 V
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Note 6) (Figures 5 and 7)
V
th
V
IH
V
IL
V
ISE
VREFAC
V
REFAC
Output Reference Voltage @ 100
mA
for capacitor− coupled inputs, only
V
CC
= 2.5 V
(Note 8) V
CC
= 1.8 V
V
CC
– 850
V
CC
– 750
V
CC
– 500
V
CC
– 450
mV
Input Threshold Reference Voltage Range (Note 7)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Single−Ended Input Voltage (V
IH
−
V
IL
)
1050
V
th
+ 100
GND
200
V
CC
−
100
V
CC
V
th
−
100
1200
mV
mV
mV
mV
V
CC
– 30
2470
1770
V
CC
– 600
1900
V
CC
– 550
1250
V
CC
– 1
2490
1790
V
CC
– 500
2000
V
CC
– 450
1350
V
CC
2500
1800
V
CC
– 400
2100
V
CC
– 350
1450
mV
V
OL
Output LOW Voltage (Note 5)
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 6 and 9) (Note 9)
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
R
TOUT
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input Common Mode Range (Differential Configuration, Note 10) (Fig-
ure 9)
Input HIGH Current (VTCLK/VTCLK Open)
Input LOW Current (VTCLK/VTCLK Open)
1100
GND
100
1050
−150
−150
V
CC
V
CC
−
100
1200
V
CC
−
50
150
150
mV
mV
mV
mV
uA
uA
CONTROL INPUT
(Reset Pin)
Input HIGH Voltage for Control Pin
Input LOW Voltage for Control Pin
Input HIGH Current
Input LOW Current
V
CC
−
200
GND
−150
−150
V
CC
200
150
150
mV
mV
uA
uA
TERMINATION RESISTORS
Internal Input Termination Resistor (@ 10 mA)
Internal Output Termination Resistor (@ 10 mA)
45
45
50
50
55
55
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
.
5. CML outputs loaded with 50
W
to V
CC
for proper operation.
6. V
th
, V
IH
, V
IL
and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
REFAC
will not be less than GND + 1050 mV.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
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NB7V32M
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
Table 6. AC CHARACTERISTICS
V
CC
= 1.71 V to 2.625 V; GND = 0 V; T
A
=
−40°C
to 85°C (Note 11)
Symbol
f
MAX
V
OUTPP
t
PLH
,
t
PHL
t
PLH
TC
t
skew
t
RR
t
PW
t
DC
t
JITTER
V
INPP
t
r,
t
f
Characteristic
Maximum Input Clock Frequency
Output Voltage Amplitude (@ V
INPPmin
)
(Note 12) (Figure 3)
Propagation Delay to Differential Outputs, @
1 GHz, measured at differential cross−point
Propagation Delay Temperature Coefficient
Duty Cycle Skew (Note 13)
Device
−
Device skew (t
pdmax
– t
pdmin
)
Reset Recovery (See Figure 11)
Minimum Pulse Width R
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
in
v
10 GHz
RJ – Output Random Jitter (Note 14) f
in
v
10 GHz
Input Voltage Swing (Differential Configuration) (Figure 10) (Note 15)
Output Rise/Fall Times @ 1 GHz (20%
−
80%), Q, Q
100
35
300
500
45
135
200
50
0.2
55
0.8
1200
60
%
ps
RMS
mV
ps
f
in
≤
10GHz
CLK/CLK to Q, Q
R to Q, Q
Min
10
280
150
400
200
200
50
20
50
275
Typ
Max
Unit
GHz
mV
ps
Dfs/°C
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 1 GHz, V
INPP
min, 50% duty−cycle clock source. All output loading with external 50
W
to V
CC
. Input edge rates 40 ps
(20%
−
80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point
of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw−
and T
pw+
@ 1 GHz. Skew
is measured between outputs under identical transitions and conditions.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Input voltage swing is a single−ended measurement operating in differential mode.
500
OUTPUT VOLTAGE AMPLITUDE
(mV)
450
Q AMP (mV)
400
350
300
250
200
0
2
4
6
8
10
VTCLK
fin, Clock Input Frequency (GHz)
CLK
50
W
CLK
I
VTCLK
50
W
R
C
R
C
V
CC
Figure 3. CLOCK Output Voltage Amplitude
(V
OUTPP
) vs. Input Frequency (f
in
) at Ambient
Temperature (Typ)
Figure 4. Input Structure
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