CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB
®
FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller
Features
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❐
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Two data pointers
3.3-V operation with 5-V tolerant inputs
Vectored USB interrupts and GPIF/FIFO interrupts
Separate data buffers for the setup and data portions of a
CONTROL transfer
Integrated I
2
C controller; runs at 100 or 400 kHz
Four integrated FIFOs
❐
Integrated glue logic and FIFOs lower system cost
❐
Automatic conversion to and from 16-bit buses
❐
Master or slave operation
❐
Uses external clock or asynchronous strobes
❐
Easy interface to ASIC and DSP ICs
Available in commercial and industrial temperature grades
(all packages except VFBGA)
USB 2.0 USB IF Hi-Speed certified (TID # 40460272)
Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
Fit-, form-, and function-compatible with the FX2
❐
Pin-compatible0
❐
Object-code-compatible
❐
Functionally compatible (FX2LP is a superset)
Ultra-low power: I
CC
no more than 85 mA in any mode
❐
Ideal for bus- and battery-powered applications
Software: 8051 code runs from:
❐
Internal RAM, which is downloaded through USB
❐
Internal RAM, which is loaded from EEPROM
❐
External memory device (128-pin package)
16 KB of on-chip code/data RAM
Four programmable BULK, INTERRUPT, and
ISOCHRONOUS endpoints
❐
Buffering options: Double, triple, and quad
Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
8-bit or 16-bit external data interface
Smart media standard ECC generation
GPIF™ (general programmable interface)
❐
Enables direct connection to most parallel interfaces
❐
Programmable waveform descriptors and configuration
registers to define waveforms
❐
Supports multiple ready (RDY) inputs and control (CTL)
outputs
Integrated, industry-standard, enhanced 8051
❐
48-MHz, 24-MHz, or 12-MHz CPU operation
❐
Four clocks per instruction cycle
❐
Two USARTs
❐
Three counter/timers
❐
Expanded interrupt system
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Features (CY7C68013A/14A only)
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CY7C68014A: Ideal for battery-powered applications
❐
Suspend current: 100
A
(typ)
CY7C68013A: Ideal for nonbattery-powered applications
❐
Suspend current: 300
A
(typ)
Available in five Pb-free packages with up to 40 GPIOs
❐
128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin
VFBGA (24 GPIOs)
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Features (CY7C68015A/16A only)
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CY7C68016A: Ideal for battery-powered applications
❐
Suspend current: 100
A
(typ)
CY7C68015A: Ideal for nonbattery-powered applications
❐
Suspend current: 300
A
(typ)
Available in Pb-free 56-pin QFN package (26 GPIOs)
Two more GPIOs than CY7C68013A/14A enabling additional
features in the same footprint
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For a complete list of related resources, click
here.
Errata:
For information on silicon errata, see
“Errata”
on page 64. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-08032 Rev. AA
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 9, 2017
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the application note
AN65209 - Getting
Started with FX2LP.
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Overview:
USB Portfolio, USB Roadmap
USB 2.0 Product Selectors:
FX2LP, AT2LP, NX2LP-Flex, SX2
EZ-USB FX2LP Development Kit
The
CY3684 EZ-USB FX2LP Development Kit
is a complete
development resource for FX2LP. It provides a platform to
develop and test custom projects using FX2LP. The
development kit contains collateral materials for the firmware,
hardware, and software aspects of a design using FX2LP.
GPIF™ Designer
FX2LP™ General Programmable Interface (GPIF) provides an
independent hardware unit, which creates the data and control
signals required by an external interface. FX2LP GPIF Designer
allows users to create and modify GPIF waveform descriptors for
EZ-USB FX2/ FX2LP family of chips using a graphical user
interface. Extensive discussion of general GPIF discussion and
programming using GPIF Designer is included in
FX2LP
Technical Reference Manual
and
GPIF Designer User Guide,
distributed with GPIF Designer.
AN66806
- Getting Started with
EZ-USB
®
FX2LP™ GPIF
can be a good starting point.
Application notes: Cypress offers a large number of USB appli-
cation notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with FX2LP are:
❐
AN65209
- Getting Started with FX2LP
®
❐
AN15456
- Guide to Successful EZ-USB FX2LP™ and
EZ-USB FX1™ Hardware Design and Debug
®
❐
AN50963
- EZ-USB FX1™/FX2LP™ Boot Options
®
❐
AN66806
- EZ-USB FX2LP™ GPIF Design Guide
❐
AN61345
- Implementing an FX2LP™- FPGA Interface
❐
AN57322
- Interfacing SRAM with FX2LP over GPIF
❐
AN4053
- Streaming Data through Isochronous/Bulk End-
points on EZ-USB
®
FX2 and EZUSB FX2LP
®
❐
AN63787
- EZ-USB FX2LP™ GPIF and Slave FIFO Con-
figuration Examples using 8-bit Asynchronous Interface
For complete list of Application notes,
click here.
Code Examples:
❐
USB Hi-Speed
Technical Reference Manual (TRM):
❐
EZ-USB FX2LP Technical Reference Manual
Reference Designs:
❐
CY4661 - External USB Hard Disk Drives (HDD) with Finger-
print Authentication Security
❐
FX2LP DMB-T/H TV Dongle reference design
Models:
IBIS
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Document Number: 38-08032 Rev. AA
Page 2 of 68
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Logic Block Diagram
24 MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
Address (16)
Data (8)
FX2LP
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
Master
Additional I/Os (24)
I
2
C
1.5k
connected for
full speed
D+
D–
Integrated
full speed and
high speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
16 KB
RAM
Abundant I/O
including two USARTs
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
4 kB
FIFO
8/16
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Cypress’s EZ-USB
®
FX2LP (CY7C68013A/14A) is a
low-power version of the EZ-USB FX2(CY7C68013), which is
a highly integrated, low-power USB 2.0 microcontroller. By
integrating the USB 2.0 transceiver, serial interface engine (SIE),
enhanced 8051 microcontroller, and a programmable peripheral
interface in a single chip, Cypress has created a cost-effective
solution that provides superior time-to-market advantages with
low power to enable bus-powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second (the maximum allowable
USB 2.0 bandwidth), while still using a low-cost 8051
microcontroller in a package as small as a 56 VFBGA (5 mm x
5 mm). Because it incorporates the USB 2.0 transceiver, the
FX2LP is more economical, providing a smaller-footprint solution
than a USB 2.0 SIE or external transceiver implementations.
With EZ-USB FX2LP, the Cypress Smart SIE handles most of
the USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application-specific functions and decreasing
the development time to ensure USB compatibility.
The general programmable interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form, and function
compatible with the 56-, 100-, and 128-pin FX2.
Five packages are defined for the family: 56 VFBGA, 56 SSOP,
56 QFN, 100 TQFP, and 128 TQFP.
Document Number: 38-08032 Rev. AA
Page 3 of 68
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Contents
Applications ...................................................................... 5
Functional Overview ........................................................ 5
USB Signaling Speed .................................................. 5
8051 Microprocessor ................................................... 5
I
2
C Bus ........................................................................ 5
Buses .......................................................................... 5
Reset and Wakeup ...................................................... 9
Program/Data RAM ................................................... 10
External FIFO Interface ............................................. 13
GPIF .......................................................................... 14
ECC Generation
[8] ................................................................... 14
USB Uploads and Downloads ................................... 14
Autopointer Access ................................................... 15
I
2
C Controller ............................................................. 15
CY7C68013A/14A and CY7C68015A/
16A Differences ......................................................... 15
Register Summary .......................................................... 32
Absolute Maximum Ratings .......................................... 39
Operating Conditions ..................................................... 39
Thermal Characteristics ................................................. 39
DC Characteristics ......................................................... 40
AC Electrical Characteristics ........................................ 41
USB Transceiver ....................................................... 41
Program Memory Read ............................................. 41
Data Memory Read
...................................................................42
Data Memory Write
..................................................................43
PORTC Strobe Feature Timings ............................... 44
Slave FIFO Synchronous Read ................................. 46
Slave FIFO Synchronous Write ................................. 48
Ordering Information ...................................................... 56
Ordering Code Definitions ......................................... 56
Package Diagrams .......................................................... 57
Quad Flat Package No Leads (QFN)
Package Design Notes ................................................... 63
Acronyms ........................................................................ 64
Document Conventions ................................................. 64
Units of Measure ....................................................... 64
Errata ............................................................................... 65
Document History Page ................................................. 66
Sales, Solutions, and Legal Information ...................... 69
Worldwide Sales and Design Support ....................... 69
Products .................................................................... 69
PSoC® Solutions ...................................................... 69
Cypress Developer Community ................................. 69
Technical Support ..................................................... 69
Document Number: 38-08032 Rev. AA
Page 4 of 68
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Applications
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Figure 1. Crystal Configuration
C1
12 pF
24 MHz
C2
12 pF
Portable video recorder
MPEG/TV conversion
DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Cameras
Scanners
Wireless LAN
MP3 players
Networking
20 × PLL
12-pF capacitor values assume a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
The CLKOUT pin, which can be three-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
USARTs
FX2LP contains two standard 8051 USARTs, addressed through
Special Function Register (SFR) bits. The USART interface pins
are available on separate I/O pins, and are not multiplexed with
port pins.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and
12 MHz) such that it always presents the correct frequency for
the 230-KBaud operation.
[1]
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in
Table 1 on page 6.
Bold type indicates nonstandard,
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit-addressable registers. The four I/O ports A to
D use the SFR addresses used in the standard 8051 for ports 0
to 3, which are not implemented in FX2LP. Because of the faster
and more efficient SFR addressing, the FX2LP I/O ports are not
addressable in external RAM space (using the MOVX
instruction).
The “Reference Designs” section of the
Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Visit
www.cypress.com
for more information.
Functional Overview
USB Signaling Speed
FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
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Full speed, with a signaling bit rate of 12 Mbps
High speed, with a signaling bit rate of 480 Mbps
FX2LP does not support the Low Speed signaling mode of
1.5 Mbps.
8051 Microprocessor
The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
8051 Clock Frequency
FX2LP has an on-chip oscillator circuit that uses an external
24-MHz (±100 ppm) crystal with the following characteristics:
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I
2
C Bus
FX2LP supports the I
2
C bus as a master only at 100/400 kHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3 V, even if no I
2
C
device is connected.
Parallel resonant
Fundamental mode
500-W drive level
12-pF (5% tolerance) load capacitors
Buses
All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,
multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz,
as required by the transceiver/PHY; internal counters divide it
down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Note
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
Document Number: 38-08032 Rev. AA
Page 5 of 68
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