NB6L239
2.5V / 3.3V Any Differential
Clock IN to Differential
LVPECL OUT
÷1/2/4/8,
÷2/4/8/16
Clock Divider
Description
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MARKING DIAGRAM*
16
1
The NB6L239 is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios;
B1/2/4/8
and
B2/4/8/16.
Both divider circuits drive a pair of differential
LVPECL outputs. (More device information on page 7). The
NB6L239 is a member of the ECLinPS MAX™ Family of the high
performance clock products.
Features
1
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
NB6L
239
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Clock Input Frequency, 3.0 GHz
CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL
EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS
Rise/Fall Time 65 ps Typical
< 10 ps Typical Output−to−Output Skew
Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
Internal 50
W
Termination Provided
Random Clock Jitter < 1 ps RMS
QA
B1
Edge Aligned to QBBn Edge
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Master Reset for Synchronization of Multiple Chips
V
BBAC
Reference Output
Synchronous Output Enable/Disable
These Devices are Pb−Free and are RoHS Compliant
SELA0
SELA1
CLK
VT
CLK
50
W
50
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
B1
B2
A
B4
B8
QA
QA
V
BBAC
EN
SELB0
SELB1
MR
+
B2
B
B4
B8
B16
QB
QB
Figure 1. Simplified Logic Diagram
1
Publication Order Number:
NB6L239/D
©
Semiconductor Components Industries, LLC, 2013
January, 2013
−
Rev. 6
NB6L239
MR
16
VT
CLK
CLK
V
BBAC
1
2
NB6L239
3
4
5
EN
6
7
8
10
9
SELA0 SELA1 V
CC
15
14
13
12
11
QA
QA
QB
QB
SELB0 SELB1 V
EE
Exposed Pad (EP)
Figure 2. Pinout: QFN−16
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
VT
CLK
CLK
V
BBAC
EN*
SELB0*
SELB1*
V
EE
QB
QB
QA
QA
V
CC
SELA1*
SELA0*
MR**
EP
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
Power Supply
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
Power Supply
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
Power Supply (OPT)
LVPECL, CML, LVDS,
HCSL, HSTL Input
LVPECL, CML, LVDS,
HCSL, HSTL Input
I/O
Description
Internal 100
W
Center−Tapped Termination Pin for CLK and CLK.
Noninverted Differential CLOCK Input.
Inverted Differential CLOCK Input.
Output Voltage Reference for Capacitor Coupled Inputs, Only.
Synchronous Output Enable
Clock Divide Select Pin
Clock Divide Select Pin
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
−
2.0 V.
Noninverted Differential Output. Typically terminated with 50
W
resistor to V
CC
−
2.0 V.
Inverted Differential Output. Typically terminated with 50
W
resistor to V
CC
−
2.0 V.
Noninverted Differential Output. Typically terminated with 50
W
resistor to V
CC
−
2.0 V.
Positive Supply Voltage.
Clock Divide Select Pin
Clock Divide Select Pin
Master Reset Asynchronous, Default Open High, Asserted LOW
The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The pad is electrically connected to the die, and
is recommended to be electrically and thermally connected to V
EE
on the PC board.
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
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2
NB6L239
+
SELA0
V
CC
SELA1
B1
B2
B4
R
B8
CLK
VT
CLK
50
W
50
W
A
QA
QA
R
B2
B
EN
SELB0
SELB1
MR
V
BBAC
B4
B8
B16
QB
QB
+
V
EE
Figure 3. Logic Diagram
Table 2. FUNCTION TABLE
CLK
EN*
L
H
X
MR**
H
H
L
FUNCTION
Divide
Hold Q
Reset Q
X
Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS
SELA1*
L
L
H
H
SELA0*
L
H
L
H
QA Outputs
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS
SELB1*
L
L
H
H
SELB0*
L
H
L
H
QB Outputs
Divide by 2
Divide by 4
Divide by 8
Divide by 16
= Low−to−High Transition
= High−to−Low Transition
X = Don’t Care
*Pins will default LOW when left OPEN.
**Pins will default HIGH when left OPEN.
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3
NB6L239
Table 5. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
75 kW
75 kW
> 1500 V
> 150 V
> 1000 V
Pb−Free Pkg
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
367
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
MAXIMUM RATINGS
Symbol
V
CC
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Input Voltage
Output Current
V
BBAC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
Standard Board
Parameter
Positive Mode Power Supply
Condition 1
V
EE
= 0 V
V
EE
= 0 V
Continuous
Surge
V
EE
v
V
I
v
V
CC
Condition 2
Rating
3.6
3.6
50
100
±
0.5
−40
to +85
−65
to +150
41.6
35.2
4.0
265
Unit
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
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4
NB6L239
Table 6. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V)
−405C
Symbol
I
EE
V
OH
Characteristic
Power Supply Cur-
rent
Output HIGH
Voltage (Notes 2, 3)
V
CC
= 3.3 V
V
CC
= 2.5 V
Output LOW Voltage
(Notes 2, 3)
V
CC
= 3.3 V
V
CC
= 2.5 V
Min
30
V
CC
−1150
2150
1350
V
CC
−1935
1365
565
Typ
40
V
CC
−1060
2240
1440
V
CC
−1775
1525
725
Max
50
V
CC
−950
2350
1550
V
CC
−1630
1670
870
Min
30
V
CC
−1100
2200
1400
V
CC
−1875
1430
630
255C
Typ
40
V
CC
−1015
2285
1485
V
CC
−1735
1565
765
Max
50
V
CC
−
900
2400
1600
V
CC
−1580
1720
920
Min
30
V
CC
−1050
2250
1450
V
CC
−1810
1490
690
85°C
Typ
40
V
CC
−980
2320
1520
V
CC
−1675
1625
825
Max
50
V
CC
−
850
2450
1650
V
CC
−1530
1770
970
mV
Unit
mA
mV
V
OL
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Figures 7, 10)
V
th
Input Threshold Ref-
erence Voltage
(Note 4)
Single−ended Input
HIGH Voltage
Single−ended Input
LOW Voltage
Output Voltage Ref-
erence @ 100
mA
(Note 7)
V
CC
= 3.3 V
V
CC
= 2.5 V
100
V
CC
−
100
100
V
CC
−
100
100
V
CC
−
100
mV
V
IH
V
IL
V
BBAC
V
th
+ 100
V
EE
V
CC
−1460
1840
1040
V
CC
−1330
1970
1170
V
CC
V
th
−
100
V
CC
−1200
2100
1300
V
th
+ 100
V
EE
V
CC
−1460
1840
1040
V
CC
−1340
1960
1160
V
CC
V
th
−
100
V
CC
−1200
2100
1300
V
th
+ 100
V
EE
V
CC
−1460
1840
1040
V
CC
−1350
1950
1150
V
CC
V
th
−
100
V
CC
−1200
2100
1300
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY
(Figures 8, 9, 11) (Note 6)
V
IHD
V
ILD
V
CMR
Differential Input
HIGH Voltage
Differential Input
LOW Voltage
Input Common
Mode Range (Differ-
ential Cross−point
Voltage) (Note 5)
Differential Input
Voltage (V
IHD(CLK)
−
V
ILD(CLK)
) and
(V
IHD(CLK)
−V
ILD(CLK)
)
Internal Input Ter-
mination Resistor
100
V
EE
50
V
CC
V
CC
– 100
V
CC
– 50
100
V
EE
50
V
CC
V
CC
– 100
V
CC
– 50
100
V
EE
50
V
CC
V
CC
– 100
V
CC
– 50
mV
mV
mV
V
ID
100
V
CC
−
V
EE
100
V
CC
−
V
EE
100
V
CC
−
V
EE
mV
R
TIN
45
50
55
45
50
55
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
.
3. Outputs loaded with 50
W
to V
CC
– 2.0 V for proper operation.
4. V
th
is applied to the complementary input when operating in single−ended mode.
5. VCMR
MIN
varies 1:1 with V
EE
, VCMR
MAX
varies 1:1 with V
CC
.
6. Input and output voltage swing is a single−ended measurement operating in differential mode.
7. V
BBAC
used to rebias capacitor−coupled inputs only (see Figures 16 and 17).
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