Features ..................................................................................................................................................... 8
Overall Features ...................................................................................................................................................8
Serial ATA Features .............................................................................................................................................8
C Pins...................................................................................................................................................20
Serial ATA Signals..............................................................................................................................................20
Test Pins ............................................................................................................................................................21
SiI3124A S-ATA Port Block Diagram..................................................................................................... 26
Data Structures ....................................................................................................................................... 27
The Command Slot.............................................................................................................................................27
The Scatter/Gather Entry (SGE).........................................................................................................................28
The Scatter/Gather Table (SGT) ........................................................................................................................29
The Port Request Block (PRB)...........................................................................................................................29
The PRB Control Field........................................................................................................................................31
The PRB Protocol Override Field .......................................................................................................................32
Standard ATA Command PRB Structure............................................................................................................33
Reset and Initialization .......................................................................................................................................39
Port Ready .........................................................................................................................................................40
Port Reset Operation..........................................................................................................................................40
Command Completion – The Slot Status Register .............................................................................................44
The Attention Bit .................................................................................................................................................45
Interrupt Service Procedure................................................................................................................................45
Interrupt No Clear on Read ................................................................................................................................45
Auto-Initialization from Flash................................................................................................................. 48
Auto-Initialization from EEPROM .......................................................................................................... 49
PCI Configuration Space ........................................................................................................................ 50
Device ID – Vendor ID........................................................................................................................................51
PCI Status – PCI Command...............................................................................................................................51
PCI Class Code – Revision ID............................................................................................................................52
BIST – Header Type – Latency Timer – Cache Line Size ..................................................................................53
Base Address Register 0....................................................................................................................................53
Base Address Register 1....................................................................................................................................54
Base Address Register 2....................................................................................................................................54
Subsystem ID – Subsystem Vendor ID ..............................................................................................................55
Expansion ROM Base Address ..........................................................................................................................55
MSI Message Data .............................................................................................................................................59
Power Management Capability...........................................................................................................................59
Power Management Control + Status.................................................................................................................59
Port Slot Status Registers ..................................................................................................................................61
Global Control ....................................................................................................................................................61
Global Interrupt Status........................................................................................................................................62
BIST Control Register.........................................................................................................................................63
BIST Status Register ..........................................................................................................................................64
Flash Memory Data / GPIO Control....................................................................................................................65
I
2
C Address ........................................................................................................................................................65
I
2
C Data / Control ...............................................................................................................................................66
Port LRAM..........................................................................................................................................................68
Port Slot Status ..................................................................................................................................................68
Port Control Set ..................................................................................................................................................69
Port Status..........................................................................................................................................................70
Port Control Clear...............................................................................................................................................70
Port Interrupt Status ...........................................................................................................................................70
Port Interrupt Enable Set / Port Interrupt Enable Clear.......................................................................................72
Port Command Execution FIFO .........................................................................................................................72
Port Command Error ..........................................................................................................................................73
Port FIS Configuration ........................................................................................................................................75
Port PCI(X) Request FIFO Threshold.................................................................................................................76
Port 8B/10B Decode Error Counter ....................................................................................................................76
Port CRC Error Counter .....................................................................................................................................77
Port Handshake Error Counter ...........................................................................................................................77
Port PHY Configuration ......................................................................................................................................78
Port Device Status Register ...............................................................................................................................78
Port Device QActive Register .............................................................................................................................79
Port Context Register .........................................................................................................................................79
Internal Register Space – Base Address 2 ........................................................................................... 83
Global Register Offset ........................................................................................................................................83
Global Register Data ..........................................................................................................................................83
Port Register Offset ............................................................................................................................................83
Port Register Data ..............................................................................................................................................83
8
9
Power Management........................................................................................................................84
Flash, GPIO, EEPROM, and I
2
C Programming.............................................................................85
C Operation ........................................................................................................................................... 86
PCI Direct Access...............................................................................................................................................85
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