Chip Schottky Barrier Diodes
FM220 THRU FM2100
Silicon epitaxial planer type
Formosa MS
SMA
0.185(4.8)
0.177(4.4)
0.012(0.3) Typ.
Features
Plastic package has Underwriters Laboratory
Flammability Classification 94V-O Utilizing Flame
Retardant Epoxy M
olding Compound.
For surface mounted applications.
Exceeds environmental standards of MIL-S-19500 /
228
Low leakage current.
0.067(1.7)
0.060(1.5)
0.110(2.8)
0.094(2.4)
0.165(4.2)
0.150(3.8)
0.040(1.0) Typ.
0.040 (1.0) Typ.
Mechanical data
Case : Molded plastic, JEDEC DO-214AC
Terminals : Solder plated, solderable per MIL-STD-750,
Method 2026
Polarity : Indicated by c athode band
Mounting P
osition : Any
Weight : 0.0017 ounce, 0.057 gram
Dimensions in inches and (millimeters)
MAXIMUM RATINGS
(AT T
A
=25
o
C unless otherwise noted)
PARAMETER
Forward rectified current
Forward surge current
See Fig.1
8.3ms single half sine-wave superimposed on
rate load (JEDEC methode)
V
R
= V
RRM
T
A
=
25
o
C
o
CONDITIONS
Symbol
I
O
I
FSM
MIN.
TYP.
MAX.
2.0
50
0.5
10
UNIT
A
A
mA
mA
o
Reverse current
Thermal resistance
Diode junction capacitance
Storage temperature
I
R
Rq
JA
C
J
T
STG
-55
75
160
V
R
= V
RRM
T
A
= 125 C
Junction to ambient
f=1MHz and applied 4vDC reverse voltage
C / w
pF
+150
o
C
SYMBOLS
MARKING
CODE
SK22
SK23
SK24
SK25
SK26
SK28
S210
V
RRM
20
30
40
50
60
80
*1
V
RMS
14
21
28
35
42
56
70
*2
V
R
*3
V
F
*4
Operating
temperature
(
o
C)
(V)
FM220
FM230
FM240
FM250
FM260
FM280
FM2100
(V)
(V)
20
30
40
50
60
80
100
(V)
0.50
-55 to +125
*1 Repetitive peak reverse voltage
0.70
-55 to +150
0.85
*2 RMS voltage
*3 Continuous reverse voltage
*4 Maximum forward voltage
100
RATING AND CHARACTERISTIC CURVES (FM220 THRU FM2100)
FIG.1-TYPICAL FORWARD CURRENT DERATING CURVE
AVERAGE FORWARD CURRENT,(A)
FIG.2-TYPICAL FORWARD
CHARACTERISTICS
2.4
2.0
50
INSTANTANEOUS FORWARD CURRENT,(A)
1.6
25
FM
FM
22
0~
FM
24
FM
26
0~
FM
28
0
0~
FM
21
00
FM
25
1.2
0.8
0.4
0
0
20
40
60
80
10
3.0
1.0
100
120
140
160
180
200
AMBIENT TEMPERATURE,( C)
0
FIG.3-MAXIMUM NON-REPETITIVE FORWARD
SURGE CURRENT
50
22
FM
24
FM
0~
0
21
FM
0~
00
Tj=25 C
Pulse Width 300us
1% Duty Cycle
0.1
PEAK FORWARD SURGE CURRENT,(A)
40
.01
.1
.3
.5
.7
.9
1.1
1.3
1.5
30
Tj=25 C
8.3ms Single Half
Sine Wave
JEDEC method
FORWARD VOLT
AGE,(V)
20
10
FIG.5 - TYPICAL REVERSE
0
1
5
10
50
100
CHARACTERISTICS
100
NUMBER OF CYCLES AT 60Hz
FIG.4-TYPICAL JUNCTION CAPACITANCE
700
600
500
400
300
200
100
0
JUNCTION CAPACITANCE,(pF)
REVERSE LEAKAGE CURRENT, (mA)
10
1.0
Tj=75 C
.1
Tj=25 C
.01
.05
.1
.5
1
5
10
50
100
.01
0
20
40
60
80
100 120 140
REVERSE VOLTAGE,(V)
PERCENT OF RATED PEAK REVERSE VOLTAGE,(%)
FPGA/CPLD
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