sames
FEATURES
s
Generates PBX supervisory tones in
PCM format
s
s
s
s
SA9401
UNIVERSAL PABX TONE GENERATOR
Each of these tone streams selectable
from 16 tone blocks
Seperate Intrude Tone for each pro-
gram
Choice of clock frequencies
Watchdog facility
Low power CMOS technology
Integrated time slot allocation circuitry
No noticeable level changes in tones
Frame synch. signal source (internal/
external) selectable
Eight tone programs
Eight independent PCM tone streams
within each program
s
s
s
s
s
s
PROGRAMMABLE FEATURES
s
Tone samples
s
s
s
s
s
s
Intrude tone frequency
Intrude tone cadence
"silence sample" value
Tone Cadence timing
Tone to time-slot mapping
Size of tone blocks
DESCRIPTION
The SA9401 operates in conjunction with a standard EPROM to generate the system
tone plans for the PABX systems of most major countries.
The high level of programmability allows the SA9401 to satisfy a wide variety of tone
plans. Furthermore by providing three inputs to select between one of eight tone
programs during initialisation, the device effectively facilitates the design of a universally
programmable "PABX Processor Card". Because the tone program inputs are latched
at the start of each PCM frame the SA9401 minimises the possibility of glitches.
The SA9401 can also generate the PCM Frame synchronising reference signal if
required.
4092
PDS039-SA9401-001
REV. C
07-05-96
SA9401
A7
MRST
D0
D1
D2
V CC
D3
D4
D5
D6
D7
39 38
37 36 35 34 33 32
31 30 29
28
27
26
25
24
CLK_SEL
A0
A1
A2
A3
GND
A4
A5
A6
PCMFSC
CLKIN
40
41
42
43
44
1
2
3
4
5
6
SA9401
23
22
21
20
19
18
TEST
FS1
A8
A9
A11
GND
A10
A12
A13
PS2
WD_INT
7
8
9
10
11 12 13 14 15
16 17
DR-00603
Package : PLCC - 44
PIN DESCRIPTION
Pin No
1, 23
12, 34
27
6
8
10
5
11
13
15
41, 42, 43, 44,
2, 3, 4, 39, 26,
25, 22, 24,
21, 20
I/0
I
I
I
I
O
O
O
O
O
O
O
Designation
GND
VCC
FS1
CLKIN
2MCLK
8KFS
PCMFSC
INTRFRQ
INTRCAD
PCM_OUT
A0..A13
2
sames
CLKDIV2
2MCLK
PS0
8KFS
INTRFRQ
VCC
INTRCAD
PS1
PCM_OUT
WD_RST
WD_EN
Description
Supply Ground
+5V Power Supply
Frame Synchronisation (active low)
Master clock input (either 8192kHz or 2048 Khz
dependent on logic level of "CLK _SEL")
2048 kHz clock derived internally from CLKIN
8 kHz Frame Synchronisation output.
8 kHz Auxilliary Frame Synchronisation Output
Square Wave Intrude Tone
Intrude Tone Cadence Signal
Tri-state PCM Highway tone output
EPROM Address Lines
SA9401
PIN DESCRIPTION (Continued)
Pin No
37, 36, 35, 33,
32, 31, 30, 29
9, 14, 19
7
40
I/0
I
I
O
I
Designation
D0..D7
PS0, PS1,
PS2
CLKDIV2
CLK_SEL
Description
EPROM Data Lines
Program Select Inputs for Selecting
between 1 of 8 tone plans
CLKIN divided by 2 output (i.e. 4096 kHz or 1024
kHz depending on CLK_SEL input)
Selects between CKLIN of 8192 or 2048 kHz and
Synchronisation source.
0 = 8192kHz/Internal
1 = 2048kHz/External
Used for IC testing purpose. Tied Low during
normal operation.
Asynchronous Reset Pin. Resets all Internal Flip
Flops (active low)
Watchdog reset input (Rising-edge triggered) Tied
high if unused
Watchdog enable input (active low) Tied high if
unused
Watchdog output (active low, tri-state)
28
38
16
17
18
I
I
I
I
O
TEST
MRST
WD_RST
WD_EN
WD_INT
BLOCK DIAGRAM
CLKDIV2
/MRST
CLK_SEL
CLKIN
CLOCK
GENERATOR
2MCLK
8KFS
PCMFSC
WD_RST
WDENB
D[7 : 0]
WATCHDOG
TIMER
WD_INT
INTRUDE
TONE
GENERATOR
INTRFRQ
/FS1
CADENCE
TIMER
INTRCAD
PS[2 : 0]
EPROM
INTERFACE
A[13 : 0]
TEST
PCM
INTERFACE
SA9401
DR-01085
PCM_OU
sames
3
SA9401
FUNCTIONAL DESCRIPTION
The design of the SA9401 has been based on the assumption that any supervisory tone
used in a PABX (e.g. Dial tone or Busy Tone etc) can be described by a small set of
simple parameters and that the tones will be injected into a standard PCM 30 (2048kHz)
backplane in either A-law or µ-law format.
In the SA9401 a tone is created by repeating a fundamental waveform (or one of two
waveforms) which would typically be one cycle of a sinewave or alternatively may be
several cycles of a higher frequency signal (say 400 to 1000Hz) modulated by a lower
frequency signal. This Tone may then be interrupted (“Cadenced”) so that the tone is
effectively switched on and off.
The waveform shape, number of samples per cycle and the cadence can all be set by
the system designer in accordance with the related National Standards.
Once a set of tones have been described they may then be injected into the PCM
backplane. The time slot associated with each tone can be set by the system designer.
The SA9401 accommodates up to 9 different Tones to form a Tone Plan making ample
allowance for Ring, Dial, Busy, Intrude and other Tones. The set of data describing one
Tone Plan (waveforms, cadence timings, timeslots etc) is referred to as a Program and
is stored in an external EPROM which is addressed directly by the SA9401.
Up to eight Tone Plans may be stored and selected at will to accommodate products for
multi-national markets.
ARCHITECTURE
The architecture of the SA9401 consists of 6 functional blocks each of which is de-
scribed in detail in the following sections. Refer also to the block diagram.
Clock Generator
The clock generator circuit derives all the timing for the ic from either a 2048kHz or a
8192kHz clock. The desired Clock is selected by the state of the CLK_SEL pin (1 for
2048kHz and 0 for 8192kHz).
The CLK_SEL pin also determines the function of the Frame Sync pin. If CLK_SEL is
low then Internal synchronisation is assumed and FS1 should be tied high. If CLK_SEL
is high then an external Frame Synchronisation source must be connected to /FS1.
The Clock Generator comprises 5 functional blocks.
A
divide-by-4 counter
is enabled only if a 8192kHz clock is selected so that all internal
timing is based on 2048kHz. The
Time Slot Counter
keeps track of the Time Slots (0
to 31) in the PCM Frame while the bit position (0 to 7) in each time-slot is tracked by the
Bit Position Counter.
PCM frame synchronisation signals are controlled by the
Frame
Generator.
Long cadence intervals are accommodated by the
Five-ms-Timebase
which delivers a 200Hz signal which clocks the Cadence Timers.
4
sames
SA9401
Intrude Tone Generator
This module generates a square wave output based on the master clock of 2048kHz.
The Intrude Tone frequency is determined by the contents of the 16-bit
Intrude Tone
Register (INTR_LO and INTR_HI)
according to the formula:-
f
int
= 2048kHz/(2*(n+1))
where n is the content of the INTR register.
The range of values in the register (from 0 to 65535) give Intrude tones in the range
15.625Hz to 1024kHz.
Cadence Timer
In any given Tone Plan the SA9401 assumes that any or all of the 9 (8 PCM tone
streams and one squarewave Intrude Tone) tones are required to have their own inde-
pendently defined cadence. A typical cadence is illustrated in FIGURE 1 above. Each
tone is assumed to comprise up to 4 cadence periods which repeat cyclically. The
duration of each period is controlled by the
Cadence Timers
which in turn comprise
10-
bit Counters.
These timers are clocked by the five_ms_timebase generated by the
Clock Generator so that intervals of up to 5.12 seconds can be defined with a resolution
of 5ms. (10 bits => 1023: 1023*5ms = 5115ms)
ON
OFF
ON
OFF
TONE_n_A
CADO_n
DR-01086
CAD1_n
TONE_n_B
CAD2_n
CAD3_n
FIGURE 1: TONE CADENCING
The
Cadence Controller
controls the loading of the 10-bit counter and the sequencing
of the Cadence Position Counter. The duration of each period of the tone is denoted by
the parameter:-
CADm_n_LO = Period m, Tone stream n low-order 8 bits and
CADm_n_HI = Period m, Tone stream n high-order 2 bits
where 0
≤
m
≤
3 and 0
≤
n
≤
8 (8 = Intrude Tone)
The
Cadence Position Counter
keeps track of the period being generated and during
period 0 the SA9401 generates a tone based on one Tone Block (A) while during the
period 2 (if used) the samples from another Block (B) are used. During periods 1 and 3
the silence sample is transmitted. This feature allows the sound of the tone to be
altered along with the cadence.
A continuous tone is created by loading values of 1(or any non-zero value),0,0,0 into
the registers CAD0_n to CAD3_n respectively. The zero value is interpreted by the
SA9401 as an instruction to ignore the period and to process the next one. With the
register contents shown the Cadence Controller continuously processes the first (ON)
period.
5
sames
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
