HANBit
HMD8M32M16
32Mbyte(8Mx32) 72-pin F/P Mode 2K Ref. SIMM Design 5V
Part No. HMD8M32M16, HMD8M32M16G
GENERAL DESCRIPTION
The HMD8M32M16 is a 8M x 32 bit dynamic RAM high density memory module. The module consists of sixteen CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board.
A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
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Part Identification
HMD8M32M16--2048 Cycles/32ms Ref, Solder
HMD8M32M16G--2048 Cycles/32ms Ref, Gold
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Access times : 50, 60ns
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High-density 32MByte design
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Single + 5V
±0.5V
power supply
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JEDEC standard pinout
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FP(Fast Page) mode operation
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TTL compatible inputs and outputs
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FR4-PCB design
PIN
SYMBOL
PIN
PIN ASSIGNMENT
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
2
3
4
5
6
7
8
9
10
Vss
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A10
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC(A11)
Vcc
A8
A9
/RAS1
/RAS0
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NC
NC
Vss
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
NC
/W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
OPTIONS
w
Timing
50ns access
60ns access
w
Packages
72-pin SIMM
MARKING
-5
-6
M
11
12
13
14
15
16
17
18
PERFORMANCE RANGE
SPEED
-5
-6
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
90ns
110ns
tPC
35ns
40ns
SIMM TOP VIEW
Note: A11 is not used for HMD8M32M16
PIN NAMES
Pin Name
A0-A10
A0-A11
DQ0-DQ31
/W
Function
Address Input(2K Ref)
Address Input(4K Ref)
Data In/Out
Read/Write Input
Pin Name
/RAS0, /RAS1
/CAS0 - /CAS3
PD1 - PD4
Function
Row Address Strobe
Column Address Strobe
Presence Detect
Pin Name
Vss
NC
Vcc
Function
Ground
No Connection
Power(+5V)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.
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FUNCTIONAL BLOCK DIAGRAM
/CAS0
HMD8M32M16
/RAS0
/CAS
DQ1
/RAS
DQ2
U0
/OE
DQ3
/W A0-A10(A11). DQ4
DQ1
DQ2
DQ3
DQ4
U8
/CAS
/RAS
/OE
/W
/RAS1
A0-A10(A11)
/CAS
DQ1
/RAS
DQ2
U1
/OE
DQ3
/W A0-A10(A11). DQ4
/CAS1
DQ1
DQ2
DQ3
DQ4
U9
/CAS
/RAS
/OE
/W
A0-A10(A11)
/CAS
DQ1
U2
/RAS
DQ2
/OE
DQ3
/W A0-A10(A11). DQ4
DQ1
DQ2
DQ3
DQ4
U10
/CAS
/RAS
/OE
/W
A0-A10(A11)
/CAS
DQ1
/RAS
DQ2
U3
/OE
DQ3
/W A0-A10(A11). DQ4
/CAS2
DQ1
DQ2
DQ3
DQ4
U11
/CAS
/RAS
/OE
/W
A0-A10(A11)
/CAS
DQ1
U4
/RAS
DQ2
/OE
DQ3
/W A0-A10(A11). DQ4
DQ1
DQ2
DQ3
DQ4
U12
/CAS
/RAS
/OE
/W
A0-A10(A11)
/CAS
DQ1
/RAS
DQ2
U5
/OE
DQ3
/W A0-A10(A11). DQ4
/CAS3
DQ1
DQ2
DQ3
DQ4
U13
/CAS
/RAS
/OE
/W
A0-A10(A11)
/CAS
DQ1
U6
/RAS
DQ2
/OE
DQ3
/W A0-A10(A11). DQ4
DQ1
DQ2
DQ3
DQ4
U14
/CAS
/RAS
/OE
/W
A0-A10(A11)
/CAS
DQ1
U7
/RAS
DQ2
/OE
DQ3
/W A0-A10(A11). DQ4
/W
A0-A10
(A11)
DQ1
DQ2
DQ3
DQ4
/CAS
/RAS
/OE
A0-A10(A11) /W
U15
URL:www.hbe.co.kr
REV.1.0 (August.2002)
2
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
HMD8M32M16
RATING
-1V to 7.0V
-1V to 7.0V
16W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
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Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V
SS
, TA=0 to 70 o C )
PARAMETER
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
SYMBOL
Vcc
Vss
V
IH
V
IL
MIN
4.5
0
2.4
-1.0
TYP.
5.0
0
-
-
MAX
5.5
0
Vcc+1
0.8
UNIT
V
V
V
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
I
CC1
-6
I
CC2
-5
I
CC3
-6
-5
I
CC4
-6
I
CC5
-5
I
CC6
-6
I
l(L)
I
O(L)
V
OH
V
OL
I
CC2
: Standby Current ( /RAS=/CAS=V
IH
)
I
CC3
: /RAS Only Refresh Current * ( /CAS=V
IH
, /RAS, Address cycling @t
RC
=min )
URL:www.hbe.co.kr
REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
SPEED
-5
MIN
-
-
-
-
-
-
-
-
-
-
-80
-80
2.4
-
MAX
1760
1600
32
1760
1600
1440
1280
16
1760
1600
80
80
-
0.4
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
I
CC1
: Operating Current * (/RAS , /CAS , Address cycling @t
RC
=min.)
3
HANBit
I
CC4
: Fast Page Mode Current * (/RAS=V
IL
, /CAS, Address cycling @t
PC
=min )
I
CC5
: Standby Current (/RAS=/CAS=Vcc-0.2V )
I
CC6
: /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t
RC
=min )
I
IL
: Input Leakage Current (Any input 0V
≤
V
IN
≤
6.5V, all other pins not under test = 0V)
I
OL
: Output Leakage Current (Data out is disabled, 0V
≤
V
OUT
≤
5.5V
V
OH
: Output High Voltage Level (I
OH
= -5mA )
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA )
HMD8M32M16
* NOTE: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the
output open. I
CC
is specified as an average current. In I
CC1
and I
CC3
, address cad be changed maximum once
while /RAS=V
IL
. In I
CC4
, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( T
A
=25 C, Vcc = 5V, f = 1Mz )
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
MIN
-
-
-
-
-
MAX
80
112
112
112
112
UNITS
pF
pF
pF
pF
pF
o
DESCRIPTION
Input Capacitance (A0-A10)
Input Capacitance (/W)
Input Capacitance (/RAS0)
Input Capacitance (/CAS0-/CAS3)
Input/Output Capacitance (DQ0-31)
AC CHARACTERISTICS
( 0 C
≤
T
A
≤
70oC , Vcc = 5V±10%, See notes 1,2.)
-5
-6
UNIT
MIN
MAX
MIN
110
50
13
25
3
3
2
30
50
13
60
15
20
15
5
10K
45
30
10K
13
50
3
3
2
30
60
15
70
20
20
15
5
10K
50
35
10K
15
50
60
15
30
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
90
o
PARAMETER
Random read or write cycle time
Access time from /RAS
Access time from /CAS
Access time from column address
/CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
/RAS precharge time
/RAS pulse width
/RAS hold time
/CAS hold time
/CAS pulse width
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
URL:www.hbe.co.kr
REV.1.0 (August.2002)
SYMBOL
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
4
HANBit Electronics Co.,Ltd.
HANBit
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address hold referenced to /RAS
Column Address to /RAS lead time
Read command set-up time
Read command hold referenced to /CAS
Read command hold referenced to /RAS
Write command hold time
Write command hold referenced to /RAS
Write command pulse width
Write command to /RAS lead time
Write command to /CAS lead time
Data-in set-up time
Data-in hold time
Data-in hold referenced to /RAS
Refresh period
Write command set-up time
/CAS setup time (C-B-R refresh)
/CAS hold time (C-B-R refresh)
/RAS precharge to /CAS hold time
Access time from /CAS precharge
Fast page mode cycle time
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
/W to /RAS precharge time (C-B-R refresh)
/W to /RAS hold time (C-B-R refresh)
/CAS precharge(C-B-R counter test)
NOTES
t
ASR
t
RAH
t
ASC
t
CAH
t
AR
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
PC
t
CP
t
RASP
t
WRP
t
WRH
t
CPT
40
10
60
10
10
20
100K
0
10
15
5
35
0
10
0
15
50
30
0
0
0
15
50
15
15
15
0
15
50
16
HMD8M32M16
0
10
0
15
55
35
0
0
0
15
55
15
20
20
0
15
55
16
0
10
15
5
40
45
10
70
10
10
30
100K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.
An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 1TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
is greater than the specified t
RCD(max)
limit, then access time is controlled exclusively by t
CAC
.
5.
Assumes that t
RCD
≥
t
RCD(max)
6. t
AR
, t
WCR
, t
DHR
are referenced to t
RAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
URL:www.hbe.co.kr
REV.1.0 (August.2002)
5
HANBit Electronics Co.,Ltd.
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