DATA INTERCONNECT
VSC3304
8.5 Gbps 4 × 4 Crosspoint Switch
BLOCK DIAGRAM:
SWITCH
4
4
4
4
Input[0:3]
EQ
EQ
Output[0:3]
VSC3304
REGISTERS
Two-Wire Serial
F E AT U R E S :
8.5 Gbps non-return-to-zero (NRZ) data bandwidth
Fully non-blocking and multicasting switch core with per-pin signal
inversion capability
Multiple time-constant programmable input and output equalization
Wide equalization adjustment range
Fully asynchronous operation with <1 ns latency
Reconfigurable Input/Output (I/O) capability
LOS detection and forwarding
Small 7 mm × 7 mm BGA with 1.0 mm pin pitch
BENEFITS:
Transparent support for virtually all data rates and protocols
Allows complete flexibility in routing and distributing signals
Compensates for multiple impairments in a signal path
Supports all types of interconnect media: PCB, backplanes, and cable
No adjustments based on data rate or reference clock required
Customize the I/O to the application
OOB forwarding for protocols like SAS and SATA
Convenient size and pin spacing for signal routing flexibility
A P P L I C AT I O N S :
Wideband signal switching and clean-up
Line driver or receiver
Backplane signal fanout, driver, or receiver
Copper cable driver or receiver
PCB signal enhancement
High-speed signal conditioner
VPPD-01594
Revision 1.1
VSC3304
8.5 Gbps 4 × 4 Crosspoint Switch
GENERAL DESCRIPTION:
The VSC3304 is a 4-port 8.5 Gbps asynchronous
switch with advanced signal equalization designed
for high-speed serial backplanes and cable
interconnect applications. VSC3304 switches allow
multicast, loopback, and reconfigurable Input/Output
VSC3304
(I/O) capability, allowing for great flexibility in
allocating and routing signals in a broad range of applications. The
VSC3304 includes dual time-constant equalization, which significantly
reduces jitter associated with driving multigigabit signals across
backplanes and cables.
Using a fully asynchronous architecture allows any data rate or protocol on
any channel without the need for an external reference clock. This gives
the VSC3304 wire-like interoperability in virtually any application that uses
binary signaling.
The VSC3304 can also be used as a buffer that simplifies and enhances
the design of high-speed signal paths by providing signal equalization at
both inputs and outputs to reduce or reverse signal degradation due to
transmission line effects.
VSC3304 ports may be configured as either inputs or outputs without
restriction. This design provides the flexibility of using the device as a
standard 4 x 4 crosspoint, or any ratio from 1 x 7 to 7 x 1. This unique
feature allows full I/O utilization in any application that translates to a
significant reduction in chip count.
Featuring programmable input signal equalization and output
pre-emphasis, each with multiple time constants, the VSC3304 is also
ideal for countering signal degradation over a wide variety of transmission
media types and lengths.
Typical power consumption for the device is 160 mW per active channel,
and unused channels may be de-activated to save the power associated
with those ports. The output drivers for the VSC3304 also feature a wide
supply voltage range, from 1.8 V to 3.3 V, that allows flexibility in matching
the output swing to the application requirements.
The VSC3304 has a loss of signal (LOS) detector with programmable
thresholds on every input port. LOS forwarding can be enabled for each of
the outputs, which will cause the outputs to be squelched in response to a
LOS detect at the corresponding input, thereby propagating signal
envelopes through the switch.
VSC3304 programming is through a standard two-wire serial interface.
The interface address can be hardwired through static pins or through a
proprietary two-pin interface that allows for address assignment after
power-up.
For more information about signal integrity solutions, visit the Vitesse Web
site at www.vitesse.com/SI.
B A C K P L A N E A P P L I C AT I O N :
B
a
c
XAUI
k
p
l
a
n
e
Line Cards
Central Switch
ASIC/
FPGA
ASIC/
FPGA
4
VSC3304
4
VSC3304
1 Gbps to
8.5 Gbps Lanes
1 Gbps to
8.5 Gbps Lanes
S P E C I F I C AT I O N S :
8.5 Gbps non-return-to-zero (NRZ) per-channel data rate
2.5 V core; 1.8 V, 2.5 V, and 3.3 V high-speed I/O
1.2 W at 3.3 V, or 0.9 W at 2.5 V, or 0.7 W at 1.8 V
Trademarks
Vitesse, ASIC-Friendly, FibreTimer, TimeStream, Snoop Loop, Super FEC, FOCUSConnect, Meigs-II, Meigs-IIe, Lansing, Campbell-I, Barrington,
PaceMaker, HOVCAT48, HOVCAT48e, HOVCAT192, HOVCAT192e, Micro PHY, FOCUS32, FOCUS16, IQ2200, NexSAS, VersaCAT, GigaStream, HawX,
SparX, StaX, VstaX, SimpliPHY,VeriPHY, ActiPHY, XFP PRO, SFP PRO, Smart-LINK, OctalMAC, EQ Technology are trademarks in the United States and/or
other jurisdictions of Vitesse Semiconductor Corporation. All other trademarks or registered trademarks mentioned herein are the property of their respective
holders.
Copyright © 2006–2007
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or
manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is
subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by
Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent
right of any manufacturer.
TM
741 Calle Plano
Camarillo, CA 93012, USA
Tel: +1 805.388.3700
Fax: +1 805.987.5896
www.vitesse.com
sales@vitesse.com
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